mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 04:02:41 +01:00
ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
39 lines
1.2 KiB
LLVM
39 lines
1.2 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
|
|
|
; Test load/store of global value from global offset table.
|
|
@seed = common global i64 0, align 8
|
|
|
|
define void @Initrand() nounwind {
|
|
entry:
|
|
; CHECK: @Initrand
|
|
; CHECK: adrp x[[REG:[0-9]+]], _seed@GOTPAGE
|
|
; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed@GOTPAGEOFF]
|
|
; CHECK: str x{{[0-9]+}}, [x[[REG2]]]
|
|
store i64 74755, i64* @seed, align 8
|
|
ret void
|
|
}
|
|
|
|
define i32 @Rand() nounwind {
|
|
entry:
|
|
; CHECK: @Rand
|
|
; CHECK: adrp x[[REG:[0-9]+]], _seed@GOTPAGE
|
|
; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed@GOTPAGEOFF]
|
|
; CHECK: movz x[[REG3:[0-9]+]], #0x51d
|
|
; CHECK: ldr x[[REG4:[0-9]+]], [x[[REG2]]]
|
|
; CHECK: mul x[[REG5:[0-9]+]], x[[REG4]], x[[REG3]]
|
|
; CHECK: movz x[[REG6:[0-9]+]], #0x3619
|
|
; CHECK: add x[[REG7:[0-9]+]], x[[REG5]], x[[REG6]]
|
|
; CHECK: orr x[[REG8:[0-9]+]], xzr, #0xffff
|
|
; CHECK: and x[[REG9:[0-9]+]], x[[REG7]], x[[REG8]]
|
|
; CHECK: str x[[REG9]], [x[[REG]]]
|
|
; CHECK: ldr x{{[0-9]+}}, [x[[REG]]]
|
|
%0 = load i64* @seed, align 8
|
|
%mul = mul nsw i64 %0, 1309
|
|
%add = add nsw i64 %mul, 13849
|
|
%and = and i64 %add, 65535
|
|
store i64 %and, i64* @seed, align 8
|
|
%1 = load i64* @seed, align 8
|
|
%conv = trunc i64 %1 to i32
|
|
ret i32 %conv
|
|
}
|