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https://github.com/RPCS3/llvm-mirror.git
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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
246 lines
7.0 KiB
LLVM
246 lines
7.0 KiB
LLVM
; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
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define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
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; CHECK-LABEL: test_vaddv_s8:
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; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a1)
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%0 = trunc i32 %vaddv.i to i8
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ret i8 %0
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}
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define signext i16 @test_vaddv_s16(<4 x i16> %a1) {
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; CHECK-LABEL: test_vaddv_s16:
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; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a1)
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%0 = trunc i32 %vaddv.i to i16
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ret i16 %0
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}
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define i32 @test_vaddv_s32(<2 x i32> %a1) {
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; CHECK-LABEL: test_vaddv_s32:
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; 2 x i32 is not supported by the ISA, thus, this is a special case
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; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a1)
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ret i32 %vaddv.i
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}
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define i64 @test_vaddv_s64(<2 x i64> %a1) {
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; CHECK-LABEL: test_vaddv_s64:
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; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
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; CHECK-NEXT: fmov x0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a1)
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ret i64 %vaddv.i
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}
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define zeroext i8 @test_vaddv_u8(<8 x i8> %a1) {
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; CHECK-LABEL: test_vaddv_u8:
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; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1)
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%0 = trunc i32 %vaddv.i to i8
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ret i8 %0
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}
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define i32 @test_vaddv_u8_masked(<8 x i8> %a1) {
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; CHECK-LABEL: test_vaddv_u8_masked:
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; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1)
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%0 = and i32 %vaddv.i, 511 ; 0x1ff
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ret i32 %0
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}
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define zeroext i16 @test_vaddv_u16(<4 x i16> %a1) {
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; CHECK-LABEL: test_vaddv_u16:
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; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a1)
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%0 = trunc i32 %vaddv.i to i16
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ret i16 %0
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}
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define i32 @test_vaddv_u16_masked(<4 x i16> %a1) {
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; CHECK-LABEL: test_vaddv_u16_masked:
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; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a1)
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%0 = and i32 %vaddv.i, 3276799 ; 0x31ffff
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ret i32 %0
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}
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define i32 @test_vaddv_u32(<2 x i32> %a1) {
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; CHECK-LABEL: test_vaddv_u32:
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; 2 x i32 is not supported by the ISA, thus, this is a special case
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; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a1)
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ret i32 %vaddv.i
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}
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define float @test_vaddv_f32(<2 x float> %a1) {
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; CHECK-LABEL: test_vaddv_f32:
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; CHECK: faddp.2s s0, v0
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)
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ret float %vaddv.i
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}
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define float @test_vaddv_v4f32(<4 x float> %a1) {
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; CHECK-LABEL: test_vaddv_v4f32:
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; CHECK: faddp.4s [[REGNUM:v[0-9]+]], v0, v0
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; CHECK: faddp.2s s0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)
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ret float %vaddv.i
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}
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define double @test_vaddv_f64(<2 x double> %a1) {
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; CHECK-LABEL: test_vaddv_f64:
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; CHECK: faddp.2d d0, v0
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)
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ret double %vaddv.i
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}
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define i64 @test_vaddv_u64(<2 x i64> %a1) {
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; CHECK-LABEL: test_vaddv_u64:
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; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
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; CHECK-NEXT: fmov x0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a1)
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ret i64 %vaddv.i
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}
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define <1 x i64> @test_vaddv_u64_to_vec(<2 x i64> %a1) {
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; CHECK-LABEL: test_vaddv_u64_to_vec:
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; CHECK: addp.2d d0, v0
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; CHECK-NOT: fmov
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; CHECK-NOT: ins
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; CHECK: ret
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entry:
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%vaddv.i = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a1)
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%vec = insertelement <1 x i64> undef, i64 %vaddv.i, i32 0
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ret <1 x i64> %vec
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}
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define signext i8 @test_vaddvq_s8(<16 x i8> %a1) {
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; CHECK-LABEL: test_vaddvq_s8:
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; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a1)
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%0 = trunc i32 %vaddv.i to i8
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ret i8 %0
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}
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define signext i16 @test_vaddvq_s16(<8 x i16> %a1) {
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; CHECK-LABEL: test_vaddvq_s16:
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; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a1)
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%0 = trunc i32 %vaddv.i to i16
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ret i16 %0
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}
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define i32 @test_vaddvq_s32(<4 x i32> %a1) {
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; CHECK-LABEL: test_vaddvq_s32:
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; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
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; CHECK-NEXT: fmov w0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a1)
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ret i32 %vaddv.i
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}
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define zeroext i8 @test_vaddvq_u8(<16 x i8> %a1) {
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; CHECK-LABEL: test_vaddvq_u8:
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; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a1)
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%0 = trunc i32 %vaddv.i to i8
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ret i8 %0
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}
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define zeroext i16 @test_vaddvq_u16(<8 x i16> %a1) {
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; CHECK-LABEL: test_vaddvq_u16:
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; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a1)
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%0 = trunc i32 %vaddv.i to i16
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ret i16 %0
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}
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define i32 @test_vaddvq_u32(<4 x i32> %a1) {
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; CHECK-LABEL: test_vaddvq_u32:
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; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
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; CHECK-NEXT: fmov [[FMOVRES:w[0-9]+]], [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a1)
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ret i32 %vaddv.i
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}
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declare i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)
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declare i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64>)
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declare i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32>)
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declare i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32>)
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declare i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
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declare float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)
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declare float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)
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declare double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)
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