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Enable tail calls by default for (micro)MIPS(64). microMIPS is slightly more tricky than doing it for MIPS(R6) or microMIPSR6. microMIPS has two instruction encodings: 16bit and 32bit along with some restrictions on the size of the instruction that can fill the delay slot. For safe tail calls for microMIPS, the delay slot filler attempts to find a correct size instruction for the delay slot of TAILCALL pseudos. Reviewers: dsanders, vkalintris Subscribers: jfb, dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D21138 llvm-svn: 277708
35 lines
1.0 KiB
LLVM
35 lines
1.0 KiB
LLVM
; RUN: llc -march=mips -relocation-model=pic < %s | FileCheck %s
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define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
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entry:
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; CHECK-DAG: lw $[[R2:[0-9]+]], 64($sp)
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; CHECK-DAG: lw $[[R3:[0-9]+]], 68($sp)
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; CHECK-DAG: move $[[R1:[0-9]+]], $5
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; CHECK-DAG: move $[[R0:[0-9]+]], $4
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; CHECK-DAG: ori $6, ${{[0-9]+}}, 3855
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; CHECK-DAG: ori $7, ${{[0-9]+}}, 22136
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; CHECK-DAG: lw $25, %call16(ff1)
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; CHECK: jalr $25
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tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
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; CHECK-DAG: lw $25, %call16(ff2)
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; CHECK-DAG: move $4, $[[R2]]
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; CHECK-DAG: move $5, $[[R3]]
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; CHECK: jalr $25
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tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
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%sub = add nsw i32 %i, -1
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; CHECK-DAG: lw $25, %call16(ff3)
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; CHECK-DAG: sw $[[R1]], 76($sp)
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; CHECK-DAG: sw $[[R0]], 72($sp)
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; CHECK-DAG: move $6, $[[R2]]
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; CHECK-DAG: move $7, $[[R3]]
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; CHECK: jr $25
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tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind
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ret void
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}
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declare void @ff1(i32, i64)
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declare void @ff2(i64, double)
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declare void @ff3(i32, i64, i32, i64)
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