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llvm-mirror/lib/Target/Sparc
Alex Bradbury 2fa138eff6 [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h
As it stands, the OperandMatchResultTy is only included in the generated
header if there is custom operand parsing. However, almost all backends
make use of MatchOperand_Success and friends from OperandMatchResultTy for
e.g. parseRegister. This is a pain when starting an AsmParser for a new
backend that doesn't yet have custom operand parsing. Move the enum to
MCTargetAsmParser.h.

This patch is a prerequisite for D23563

Differential Revision: https://reviews.llvm.org/D23496

llvm-svn: 285705
2016-11-01 16:32:05 +00:00
..
AsmParser [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h 2016-11-01 16:32:05 +00:00
Disassembler Move the global variables representing each Target behind accessor function 2016-10-09 23:00:34 +00:00
InstPrinter
MCTargetDesc Move the global variables representing each Target behind accessor function 2016-10-09 23:00:34 +00:00
TargetInfo Move the global variables representing each Target behind accessor function 2016-10-09 23:00:34 +00:00
CMakeLists.txt
DelaySlotFiller.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
LeonFeatures.td [Sparc][LEON] Detects an erratum on UT699 LEON 3 processors involving rounding mode changes and issues an appropriate user error message. 2016-10-19 14:01:06 +00:00
LeonPasses.cpp [Sparc][LEON] Detects an erratum on UT699 LEON 3 processors involving rounding mode changes and issues an appropriate user error message. 2016-10-19 14:01:06 +00:00
LeonPasses.h [Sparc][LEON] Detects an erratum on UT699 LEON 3 processors involving rounding mode changes and issues an appropriate user error message. 2016-10-19 14:01:06 +00:00
LLVMBuild.txt
README.txt
Sparc.h
Sparc.td This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included. 2016-10-10 08:53:06 +00:00
SparcAsmPrinter.cpp Move the global variables representing each Target behind accessor function 2016-10-09 23:00:34 +00:00
SparcCallingConv.td
SparcFrameLowering.cpp
SparcFrameLowering.h
SparcInstr64Bit.td
SparcInstrAliases.td
SparcInstrFormats.td
SparcInstrInfo.cpp Finish renaming remaining analyzeBranch functions 2016-09-14 20:43:16 +00:00
SparcInstrInfo.h Finish renaming remaining analyzeBranch functions 2016-09-14 20:43:16 +00:00
SparcInstrInfo.td [Sparc] Implement UMUL_LOHI and SMUL_LOHI instead of MULHS/MULHU/MUL. 2016-10-05 20:54:17 +00:00
SparcInstrVIS.td
SparcISelDAGToDAG.cpp This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included. 2016-10-10 08:53:06 +00:00
SparcISelLowering.cpp [Sparc] Don't overlap variable-sized allocas with other stack variables. 2016-10-25 22:13:28 +00:00
SparcISelLowering.h
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcMCInstLower.cpp
SparcRegisterInfo.cpp
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSchedule.td
SparcSubtarget.cpp [Sparc][LEON] Detects an erratum on UT699 LEON 3 processors involving rounding mode changes and issues an appropriate user error message. 2016-10-19 14:01:06 +00:00
SparcSubtarget.h [Sparc][LEON] Detects an erratum on UT699 LEON 3 processors involving rounding mode changes and issues an appropriate user error message. 2016-10-19 14:01:06 +00:00
SparcTargetMachine.cpp [Sparc][LEON] Detects an erratum on UT699 LEON 3 processors involving rounding mode changes and issues an appropriate user error message. 2016-10-19 14:01:06 +00:00
SparcTargetMachine.h
SparcTargetObjectFile.cpp Move the Mangler from the AsmPrinter down to TLOF and clean up the 2016-09-16 07:33:15 +00:00
SparcTargetObjectFile.h Move the Mangler from the AsmPrinter down to TLOF and clean up the 2016-09-16 07:33:15 +00:00
SparcTargetStreamer.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.