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a62a7bb9a4
This adds all remaining instructions that were still missing, mostly privileged and semi-privileged system-level instructions. These are provided for use with the assembler and disassembler only. This brings the LLVM assembler / disassembler to parity with the GNU binutils tools. llvm-svn: 306876
79 lines
2.8 KiB
TableGen
79 lines
2.8 KiB
TableGen
//===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// SystemZ subtarget features
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//===----------------------------------------------------------------------===//
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include "SystemZFeatures.td"
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//===----------------------------------------------------------------------===//
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// SystemZ subtarget scheduling models
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//===----------------------------------------------------------------------===//
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include "SystemZSchedule.td"
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//===----------------------------------------------------------------------===//
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// SystemZ supported processors
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//===----------------------------------------------------------------------===//
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include "SystemZProcessors.td"
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//===----------------------------------------------------------------------===//
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// Register file description
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//===----------------------------------------------------------------------===//
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include "SystemZRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Calling convention description
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//===----------------------------------------------------------------------===//
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include "SystemZCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Instruction descriptions
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//===----------------------------------------------------------------------===//
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include "SystemZOperators.td"
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include "SystemZOperands.td"
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include "SystemZPatterns.td"
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include "SystemZInstrFormats.td"
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include "SystemZInstrInfo.td"
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include "SystemZInstrVector.td"
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include "SystemZInstrFP.td"
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include "SystemZInstrHFP.td"
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include "SystemZInstrDFP.td"
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include "SystemZInstrSystem.td"
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def SystemZInstrInfo : InstrInfo {}
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//===----------------------------------------------------------------------===//
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// Assembly parser
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//===----------------------------------------------------------------------===//
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def SystemZAsmParser : AsmParser {
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let ShouldEmitMatchRegisterName = 0;
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}
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//===----------------------------------------------------------------------===//
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// Top-level target declaration
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//===----------------------------------------------------------------------===//
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def SystemZ : Target {
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let InstructionSet = SystemZInstrInfo;
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let AssemblyParsers = [SystemZAsmParser];
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}
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