mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-31 07:52:55 +01:00
cf082ae903
This update was done with the following bash script:
find test/Transforms -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_]*\):\( *\)@$FUNC\([( ]*\)\$/;\1\2-LABEL:\3@$FUNC(/g" $TEMP
done
mv $TEMP $NAME
fi
done
llvm-svn: 186268
409 lines
9.8 KiB
LLVM
409 lines
9.8 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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; Check that instcombine rewrites multiply by a vector
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; of known constant power-of-2 elements with vector shift.
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define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
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entry:
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%mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @Zero_i8(
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; CHECK: ret <4 x i8> zeroinitializer
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define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
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entry:
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%mul = mul <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @Identity_i8(
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; CHECK: ret <4 x i8> %InVec
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define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
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entry:
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%mul = mul <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @AddToSelf_i8(
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; CHECK: shl <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
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; CHECK: ret
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define <4 x i8> @SplatPow2Test1_i8(<4 x i8> %InVec) {
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entry:
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%mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 4, i8 4>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @SplatPow2Test1_i8(
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; CHECK: shl <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
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; CHECK: ret
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define <4 x i8> @SplatPow2Test2_i8(<4 x i8> %InVec) {
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entry:
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%mul = mul <4 x i8> %InVec, <i8 8, i8 8, i8 8, i8 8>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @SplatPow2Test2_i8(
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; CHECK: shl <4 x i8> %InVec, <i8 3, i8 3, i8 3, i8 3>
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; CHECK: ret
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define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
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entry:
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%mul = mul <4 x i8> %InVec, <i8 1, i8 2, i8 4, i8 8>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @MulTest1_i8(
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; CHECK: shl <4 x i8> %InVec, <i8 0, i8 1, i8 2, i8 3>
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; CHECK: ret
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define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
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entry:
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%mul = mul <4 x i8> %InVec, <i8 3, i8 3, i8 3, i8 3>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @MulTest2_i8(
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; CHECK: mul <4 x i8> %InVec, <i8 3, i8 3, i8 3, i8 3>
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; CHECK: ret
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define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
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entry:
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%mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 2, i8 2>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @MulTest3_i8(
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; CHECK: shl <4 x i8> %InVec, <i8 2, i8 2, i8 1, i8 1>
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; CHECK: ret
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define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
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entry:
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%mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 0, i8 1>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @MulTest4_i8(
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; CHECK: mul <4 x i8> %InVec, <i8 4, i8 4, i8 0, i8 1>
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; CHECK: ret
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define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
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entry:
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%mul = mul <4 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @Zero_i16(
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; CHECK: ret <4 x i16> zeroinitializer
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define <4 x i16> @Identity_i16(<4 x i16> %InVec) {
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entry:
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%mul = mul <4 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @Identity_i16(
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; CHECK: ret <4 x i16> %InVec
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define <4 x i16> @AddToSelf_i16(<4 x i16> %InVec) {
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entry:
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%mul = mul <4 x i16> %InVec, <i16 2, i16 2, i16 2, i16 2>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @AddToSelf_i16(
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; CHECK: shl <4 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1>
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; CHECK: ret
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define <4 x i16> @SplatPow2Test1_i16(<4 x i16> %InVec) {
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entry:
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%mul = mul <4 x i16> %InVec, <i16 4, i16 4, i16 4, i16 4>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @SplatPow2Test1_i16(
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; CHECK: shl <4 x i16> %InVec, <i16 2, i16 2, i16 2, i16 2>
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; CHECK: ret
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define <4 x i16> @SplatPow2Test2_i16(<4 x i16> %InVec) {
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entry:
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%mul = mul <4 x i16> %InVec, <i16 8, i16 8, i16 8, i16 8>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @SplatPow2Test2_i16(
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; CHECK: shl <4 x i16> %InVec, <i16 3, i16 3, i16 3, i16 3>
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; CHECK: ret
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define <4 x i16> @MulTest1_i16(<4 x i16> %InVec) {
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entry:
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%mul = mul <4 x i16> %InVec, <i16 1, i16 2, i16 4, i16 8>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @MulTest1_i16(
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; CHECK: shl <4 x i16> %InVec, <i16 0, i16 1, i16 2, i16 3>
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; CHECK: ret
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define <4 x i16> @MulTest2_i16(<4 x i16> %InVec) {
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entry:
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%mul = mul <4 x i16> %InVec, <i16 3, i16 3, i16 3, i16 3>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @MulTest2_i16(
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; CHECK: mul <4 x i16> %InVec, <i16 3, i16 3, i16 3, i16 3>
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; CHECK: ret
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define <4 x i16> @MulTest3_i16(<4 x i16> %InVec) {
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entry:
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%mul = mul <4 x i16> %InVec, <i16 4, i16 4, i16 2, i16 2>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @MulTest3_i16(
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; CHECK: shl <4 x i16> %InVec, <i16 2, i16 2, i16 1, i16 1>
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; CHECK: ret
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define <4 x i16> @MulTest4_i16(<4 x i16> %InVec) {
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entry:
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%mul = mul <4 x i16> %InVec, <i16 4, i16 4, i16 0, i16 2>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @MulTest4_i16(
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; CHECK: mul <4 x i16> %InVec, <i16 4, i16 4, i16 0, i16 2>
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; CHECK: ret
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define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
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entry:
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%mul = mul <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @Zero_i32(
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; CHECK: ret <4 x i32> zeroinitializer
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define <4 x i32> @Identity_i32(<4 x i32> %InVec) {
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entry:
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%mul = mul <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @Identity_i32(
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; CHECK: ret <4 x i32> %InVec
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define <4 x i32> @AddToSelf_i32(<4 x i32> %InVec) {
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entry:
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%mul = mul <4 x i32> %InVec, <i32 2, i32 2, i32 2, i32 2>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @AddToSelf_i32(
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; CHECK: shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
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; CHECK: ret
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define <4 x i32> @SplatPow2Test1_i32(<4 x i32> %InVec) {
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entry:
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%mul = mul <4 x i32> %InVec, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @SplatPow2Test1_i32(
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; CHECK: shl <4 x i32> %InVec, <i32 2, i32 2, i32 2, i32 2>
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; CHECK: ret
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define <4 x i32> @SplatPow2Test2_i32(<4 x i32> %InVec) {
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entry:
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%mul = mul <4 x i32> %InVec, <i32 8, i32 8, i32 8, i32 8>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @SplatPow2Test2_i32(
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; CHECK: shl <4 x i32> %InVec, <i32 3, i32 3, i32 3, i32 3>
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; CHECK: ret
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define <4 x i32> @MulTest1_i32(<4 x i32> %InVec) {
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entry:
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%mul = mul <4 x i32> %InVec, <i32 1, i32 2, i32 4, i32 8>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @MulTest1_i32(
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; CHECK: shl <4 x i32> %InVec, <i32 0, i32 1, i32 2, i32 3>
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; CHECK: ret
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define <4 x i32> @MulTest2_i32(<4 x i32> %InVec) {
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entry:
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%mul = mul <4 x i32> %InVec, <i32 3, i32 3, i32 3, i32 3>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @MulTest2_i32(
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; CHECK: mul <4 x i32> %InVec, <i32 3, i32 3, i32 3, i32 3>
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; CHECK: ret
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define <4 x i32> @MulTest3_i32(<4 x i32> %InVec) {
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entry:
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%mul = mul <4 x i32> %InVec, <i32 4, i32 4, i32 2, i32 2>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @MulTest3_i32(
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; CHECK: shl <4 x i32> %InVec, <i32 2, i32 2, i32 1, i32 1>
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; CHECK: ret
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define <4 x i32> @MulTest4_i32(<4 x i32> %InVec) {
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entry:
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%mul = mul <4 x i32> %InVec, <i32 4, i32 4, i32 0, i32 1>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @MulTest4_i32(
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; CHECK: mul <4 x i32> %InVec, <i32 4, i32 4, i32 0, i32 1>
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; CHECK: ret
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define <4 x i64> @Zero_i64(<4 x i64> %InVec) {
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entry:
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%mul = mul <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @Zero_i64(
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; CHECK: ret <4 x i64> zeroinitializer
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define <4 x i64> @Identity_i64(<4 x i64> %InVec) {
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entry:
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%mul = mul <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @Identity_i64(
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; CHECK: ret <4 x i64> %InVec
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define <4 x i64> @AddToSelf_i64(<4 x i64> %InVec) {
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entry:
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%mul = mul <4 x i64> %InVec, <i64 2, i64 2, i64 2, i64 2>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @AddToSelf_i64(
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; CHECK: shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
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; CHECK: ret
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define <4 x i64> @SplatPow2Test1_i64(<4 x i64> %InVec) {
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entry:
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%mul = mul <4 x i64> %InVec, <i64 4, i64 4, i64 4, i64 4>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @SplatPow2Test1_i64(
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; CHECK: shl <4 x i64> %InVec, <i64 2, i64 2, i64 2, i64 2>
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; CHECK: ret
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define <4 x i64> @SplatPow2Test2_i64(<4 x i64> %InVec) {
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entry:
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%mul = mul <4 x i64> %InVec, <i64 8, i64 8, i64 8, i64 8>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @SplatPow2Test2_i64(
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; CHECK: shl <4 x i64> %InVec, <i64 3, i64 3, i64 3, i64 3>
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; CHECK: ret
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define <4 x i64> @MulTest1_i64(<4 x i64> %InVec) {
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entry:
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%mul = mul <4 x i64> %InVec, <i64 1, i64 2, i64 4, i64 8>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @MulTest1_i64(
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; CHECK: shl <4 x i64> %InVec, <i64 0, i64 1, i64 2, i64 3>
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; CHECK: ret
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define <4 x i64> @MulTest2_i64(<4 x i64> %InVec) {
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entry:
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%mul = mul <4 x i64> %InVec, <i64 3, i64 3, i64 3, i64 3>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @MulTest2_i64(
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; CHECK: mul <4 x i64> %InVec, <i64 3, i64 3, i64 3, i64 3>
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; CHECK: ret
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define <4 x i64> @MulTest3_i64(<4 x i64> %InVec) {
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entry:
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%mul = mul <4 x i64> %InVec, <i64 4, i64 4, i64 2, i64 2>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @MulTest3_i64(
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; CHECK: shl <4 x i64> %InVec, <i64 2, i64 2, i64 1, i64 1>
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; CHECK: ret
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define <4 x i64> @MulTest4_i64(<4 x i64> %InVec) {
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entry:
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%mul = mul <4 x i64> %InVec, <i64 4, i64 4, i64 0, i64 1>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @MulTest4_i64(
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; CHECK: mul <4 x i64> %InVec, <i64 4, i64 4, i64 0, i64 1>
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; CHECK: ret
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; Test also that the following rewriting rule works with vectors
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; of integers as well:
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; ((X << C1)*C2) == (X * (C2 << C1))
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define <4 x i8> @ShiftMulTest1(<4 x i8> %InVec) {
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entry:
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%shl = shl <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
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%mul = mul <4 x i8> %shl, <i8 3, i8 3, i8 3, i8 3>
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ret <4 x i8> %mul
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}
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; CHECK-LABEL: @ShiftMulTest1(
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; CHECK: mul <4 x i8> %InVec, <i8 12, i8 12, i8 12, i8 12>
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; CHECK: ret
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define <4 x i16> @ShiftMulTest2(<4 x i16> %InVec) {
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entry:
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%shl = shl <4 x i16> %InVec, <i16 2, i16 2, i16 2, i16 2>
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%mul = mul <4 x i16> %shl, <i16 3, i16 3, i16 3, i16 3>
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ret <4 x i16> %mul
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}
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; CHECK-LABEL: @ShiftMulTest2(
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; CHECK: mul <4 x i16> %InVec, <i16 12, i16 12, i16 12, i16 12>
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; CHECK: ret
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define <4 x i32> @ShiftMulTest3(<4 x i32> %InVec) {
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entry:
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%shl = shl <4 x i32> %InVec, <i32 2, i32 2, i32 2, i32 2>
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%mul = mul <4 x i32> %shl, <i32 3, i32 3, i32 3, i32 3>
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ret <4 x i32> %mul
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}
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; CHECK-LABEL: @ShiftMulTest3(
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; CHECK: mul <4 x i32> %InVec, <i32 12, i32 12, i32 12, i32 12>
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; CHECK: ret
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define <4 x i64> @ShiftMulTest4(<4 x i64> %InVec) {
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entry:
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%shl = shl <4 x i64> %InVec, <i64 2, i64 2, i64 2, i64 2>
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%mul = mul <4 x i64> %shl, <i64 3, i64 3, i64 3, i64 3>
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ret <4 x i64> %mul
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}
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; CHECK-LABEL: @ShiftMulTest4(
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; CHECK: mul <4 x i64> %InVec, <i64 12, i64 12, i64 12, i64 12>
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; CHECK: ret
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