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2221e69a13
Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
75 lines
2.0 KiB
LLVM
75 lines
2.0 KiB
LLVM
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s %s -o - | FileCheck %s --check-prefix=CHECK-DSP
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; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-NO-DSP
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; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP
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; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
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; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP
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define i32 @test0(i8 %A) {
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; CHECK-LABEL: test0:
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; CHECK-DSP: sxtb r0, r0
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; CHECK-NO-DSP: sxtb r0, r0
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%B = sext i8 %A to i32
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ret i32 %B
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}
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define signext i8 @test1(i32 %A) {
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; CHECK-LABEL: test1:
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; CHECK-DSP: sbfx r0, r0, #8, #8
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; CHECK-NO-DSP: sbfx r0, r0, #8, #8
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%B = lshr i32 %A, 8
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%C = shl i32 %A, 24
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%D = or i32 %B, %C
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%E = trunc i32 %D to i8
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ret i8 %E
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}
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define signext i32 @test2(i32 %A, i32 %X) {
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; CHECK-LABEL: test2:
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; CHECK-DSP: sxtab r0, r1, r0, ror #8
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; CHECK-NO-DSP-NOT: sxtab
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%B = lshr i32 %A, 8
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%C = shl i32 %A, 24
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%D = or i32 %B, %C
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%E = trunc i32 %D to i8
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%F = sext i8 %E to i32
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%G = add i32 %F, %X
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ret i32 %G
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}
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define i32 @test3(i32 %A, i32 %X) {
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; CHECK-LABEL: test3:
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; CHECK-DSP: sxtah r0, r0, r1, ror #8
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; CHECK-NO-DSP-NOT: sxtah
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%X.hi = lshr i32 %X, 8
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%X.trunc = trunc i32 %X.hi to i16
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%addend = sext i16 %X.trunc to i32
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%sum = add i32 %A, %addend
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ret i32 %sum
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}
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define signext i32 @test4(i32 %A, i32 %X) {
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; CHECK-LABEL: test4:
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; CHECK-DSP: sxtab r0, r1, r0, ror #16
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; CHECK-NO-DSP-NOT: sxtab
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%B = lshr i32 %A, 16
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%C = shl i32 %A, 16
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%D = or i32 %B, %C
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%E = trunc i32 %D to i8
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%F = sext i8 %E to i32
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%G = add i32 %F, %X
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ret i32 %G
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}
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define signext i32 @test5(i32 %A, i32 %X) {
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; CHECK-LABEL: test5:
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; CHECK-DSP: sxtah r0, r1, r0, ror #24
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; CHECK-NO-DSP-NOT: sxtah
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%B = lshr i32 %A, 24
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%C = shl i32 %A, 8
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%D = or i32 %B, %C
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%E = trunc i32 %D to i16
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%F = sext i16 %E to i32
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%G = add i32 %F, %X
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ret i32 %G
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}
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