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2779613cc9
This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
75 lines
4.4 KiB
TableGen
75 lines
4.4 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
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// RUN: FileCheck %s --check-prefixes=CHECK_NOPT -input-file=%T/context-non-optimized.cpp
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// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/context-optimized.cpp
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// RUN: FileCheck %s --check-prefixes=CHECK_OPT -input-file=%T/context-optimized.cpp
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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def test_atomic_op_frag : PatFrag<(ops node:$ptr, node:$val),
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(atomic_swap node:$ptr, node:$val)> {
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let GISelPredicateCode = [{ return !MRI.use_nodbg_empty(MI.getOperand(0).getReg()); }];
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let IsAtomic = 1;
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let MemoryVT = i32;
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}
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def INSN : I<(outs GPR32:$dst), (ins GPR32Op:$src1, GPR32Op:$src2), []>;
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def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) ,
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(INSN GPR32:$ptr, GPR32:$val)>;
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// CHECK_NOPT-LABEL: const int64_t *MyTargetInstructionSelector::getMatchTable() const {
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// CHECK_NOPT-NEXT: constexpr static int64_t MatchTable0[] = {
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// CHECK_NOPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 46, // Rule ID 0 //
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// CHECK_NOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// CHECK_NOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ATOMICRMW_XCHG,
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// CHECK_NOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
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// CHECK_NOPT-NEXT: // MIs[0] dst
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// CHECK_NOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK_NOPT-NEXT: // MIs[0] ptr
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// CHECK_NOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
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// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK_NOPT-NEXT: // MIs[0] val
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// CHECK_NOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK_NOPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_test_atomic_op_frag,
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// CHECK_NOPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)
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// CHECK_NOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INSN,
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// CHECK_NOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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// CHECK_NOPT-NEXT: // GIR_Coverage, 0,
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// CHECK_NOPT-NEXT: GIR_Done,
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// CHECK_NOPT-NEXT: // Label 0: @46
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// CHECK_NOPT-NEXT: GIM_Reject,
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// CHECK_NOPT-NEXT: };
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// CHECK_NOPT-NEXT: return MatchTable0;
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// CHECK_NOPT-NEXT: }
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//
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//
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// CHECK_OPT-LABEL: const int64_t *MyTargetInstructionSelector::getMatchTable() const {
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// CHECK_OPT-NEXT: constexpr static int64_t MatchTable0[] = {
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// CHECK_OPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 43, // Rule ID 0 //
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// CHECK_OPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ATOMICRMW_XCHG,
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// CHECK_OPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK_OPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK_OPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
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// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK_OPT-NEXT: // MIs[0] ptr
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// CHECK_OPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
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// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK_OPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_test_atomic_op_frag,
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// CHECK_OPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)
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// CHECK_OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INSN,
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// CHECK_OPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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// CHECK_OPT-NEXT: // GIR_Coverage, 0,
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// CHECK_OPT-NEXT: GIR_Done,
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// CHECK_OPT-NEXT: // Label 0: @43
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// CHECK_OPT-NEXT: GIM_Reject,
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// CHECK_OPT-NEXT: };
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// CHECK_OPT-NEXT: return MatchTable0;
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// CHECK_OPT-NEXT: }
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