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llvm-mirror/test/CodeGen/PowerPC/pr26180.ll
Matthias Braun aee5f0fc5d Relax fast register allocator related test cases; NFC
- Relex hard coded registers and stack frame sizes
- Some test cleanups
- Change phi-dbg.ll to match on mir output after phi elimination instead
  of going through the whole codegen pipeline.

This is in preparation for https://reviews.llvm.org/D52010
I'm committing all the test changes upfront that work before and after
independently.

llvm-svn: 345532
2018-10-29 20:10:42 +00:00

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LLVM

; RUN: llc -mcpu=generic -mtriple=powerpc64le-unknown-unknown -O0 < %s | FileCheck %s --check-prefix=GENERIC
; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s | FileCheck %s
define i32 @bad(double %x) {
%1 = fptoui double %x to i32
ret i32 %1
}
; CHECK: fctidz [[REG0:[0-9]+]], 1
; CHECK: stfd [[REG0]], [[OFF:.*]](1)
; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
; GENERIC: fctiwuz [[REG0:[0-9]+]], 1
; GENERIC: stfd [[REG0]], [[OFF:.*]](1)
; GENERIC: lwz {{[0-9]*}}, [[OFF]](1)