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f727f5bf00
Added assembler and disassembler support for the new Release Consistent processor consistent instructions, introduced with ARM v8.3-A for AArch64. Differential Revision: https://reviews.llvm.org/D36522 llvm-svn: 310575
24 lines
1.0 KiB
ArmAsm
24 lines
1.0 KiB
ArmAsm
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
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// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
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ldaprb w0, [x0, #0]
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ldaprh w0, [x17, #0]
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ldapr w0, [x1, #0]
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ldapr x0, [x0, #0]
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ldapr w18, [x0]
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ldapr x15, [x0]
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// CHECK: ldaprb w0, [x0] // encoding: [0x00,0xc0,0xbf,0x38]
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// CHECK: ldaprh w0, [x17] // encoding: [0x20,0xc2,0xbf,0x78]
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// CHECK: ldapr w0, [x1] // encoding: [0x20,0xc0,0xbf,0xb8]
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// CHECK: ldapr x0, [x0] // encoding: [0x00,0xc0,0xbf,0xf8]
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// CHECK: ldapr w18, [x0] // encoding: [0x12,0xc0,0xbf,0xb8]
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// CHECK: ldapr x15, [x0] // encoding: [0x0f,0xc0,0xbf,0xf8]
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// CHECK-REQ: error: invalid operand for instruction
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// CHECK-REQ: error: invalid operand for instruction
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// CHECK-REQ: error: invalid operand for instruction
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// CHECK-REQ: error: invalid operand for instruction
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// CHECK-REQ: error: instruction requires: rcpc
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// CHECK-REQ: error: instruction requires: rcpc
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