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llvm-mirror/test/MC/AArch64/coff-relocations.s
Martin Storsjo 3852d448a7 [COFF, ARM64] Fix symbol offsets in ADRP/ADD/LDR/STR relocations
In COFF, a symbol offset can't be stored in the relocation (as is
done in ELF or MachO), but is stored as the immediate in the
instruction itself. The immediate in the ADRP thus is the symbol
offset in bytes, not in pages. For the PAGEOFFSET_12A/L relocations,
ignore any offset outside of the lowest 12 bits; they won't have any
effect on the ADD/LDR/STR instruction itself but only on the associated
ADRP.

This is similar to how the same issue is handled for MOVW/MOVT
instructions in ELF (see e.g. SVN r307713, and r307728 in lld).

This fixes "fixup out of range" errors while building larger object
files, where temporary symbols end up as a plain section symbol and
an offset, and fixes any cases where the symbol offset mean that
the actual target ended up on a different page than the symbol
itself.

Differential Revision: https://reviews.llvm.org/D35791

llvm-svn: 309105
2017-07-26 11:19:17 +00:00

74 lines
1.9 KiB
ArmAsm

; RUN: llvm-mc -triple aarch64-windows -filetype obj -o %t.obj %s
; RUN: llvm-readobj -r %t.obj | FileCheck %s
; RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix DISASM
; IMAGE_REL_ARM64_ADDR32
.Linfo_foo:
.asciz "foo"
.long foo
; IMAGE_REL_ARM64_ADDR32NB
.long func@IMGREL
; IMAGE_REL_ARM64_ADDR64
.globl struc
struc:
.quad arr
; IMAGE_REL_ARM64_BRANCH26
b target
; IMAGE_REL_ARM64_PAGEBASE_REL21
adrp x0, foo
; IMAGE_REL_ARM64_PAGEOFFSET_12A
add x0, x0, :lo12:foo
; IMAGE_REL_ARM64_PAGEOFFSET_12L
ldr x0, [x0, :lo12:foo]
; IMAGE_REL_ARM64_PAGEBASE_REL21, even if the symbol offset is known
adrp x0, bar
bar:
; IMAGE_REL_ARM64_SECREL
.secrel32 .Linfo_bar
.Linfo_bar:
; IMAGE_REL_ARM64_SECTION
.secidx func
.align 2
adrp x0, baz + 0x12345
baz:
add x0, x0, :lo12:foo + 0x12345
ldrb w0, [x0, :lo12:foo + 0x12345]
ldr x0, [x0, :lo12:foo + 0x12348]
; CHECK: Format: COFF-ARM64
; CHECK: Arch: aarch64
; CHECK: AddressSize: 64bit
; CHECK: Relocations [
; CHECK: Section (1) .text {
; CHECK: 0x4 IMAGE_REL_ARM64_ADDR32 foo
; CHECK: 0x8 IMAGE_REL_ARM64_ADDR32NB func
; CHECK: 0xC IMAGE_REL_ARM64_ADDR64 arr
; CHECK: 0x14 IMAGE_REL_ARM64_BRANCH26 target
; CHECK: 0x18 IMAGE_REL_ARM64_PAGEBASE_REL21 foo
; CHECK: 0x1C IMAGE_REL_ARM64_PAGEOFFSET_12A foo
; CHECK: 0x20 IMAGE_REL_ARM64_PAGEOFFSET_12L foo
; CHECK: 0x24 IMAGE_REL_ARM64_PAGEBASE_REL21 bar
; CHECK: 0x28 IMAGE_REL_ARM64_SECREL .text
; CHECK: 0x2C IMAGE_REL_ARM64_SECTION func
; CHECK: 0x30 IMAGE_REL_ARM64_PAGEBASE_REL21 baz
; CHECK: 0x34 IMAGE_REL_ARM64_PAGEOFFSET_12A foo
; CHECK: 0x38 IMAGE_REL_ARM64_PAGEOFFSET_12L foo
; CHECK: 0x3C IMAGE_REL_ARM64_PAGEOFFSET_12L foo
; CHECK: }
; CHECK: ]
; DISASM: 30: 20 1a 09 b0 adrp x0, #305418240
; DISASM: 34: 00 14 0d 91 add x0, x0, #837
; DISASM: 38: 00 14 4d 39 ldrb w0, [x0, #837]
; DISASM: 3c: 00 a4 41 f9 ldr x0, [x0, #840]