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arm-tests.txt
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Specify cpu to unbreak tests.
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2012-04-26 01:38:10 +00:00 |
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basic-arm-instructions.txt
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Specify cpu to unbreak tests.
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2012-04-26 01:38:10 +00:00 |
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fp-encoding.txt
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Fixed disassembler for vstm/vldm ARM VFP instructions.
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2012-05-03 16:38:40 +00:00 |
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invalid-Bcc-thumb.txt
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Tighten Thumb1 branch predicate decoding.
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2011-08-09 21:07:45 +00:00 |
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invalid-BFI-arm.txt
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Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
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2011-08-09 22:48:45 +00:00 |
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invalid-CPS2p-arm.txt
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Tighten operand checking on CPS instructions.
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2011-08-09 23:05:39 +00:00 |
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invalid-CPS3p-arm.txt
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Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
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2011-10-28 18:02:13 +00:00 |
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invalid-DMB-thumb.txt
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Tighten operand checking on memory barrier instructions.
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2011-08-09 23:25:42 +00:00 |
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invalid-DSB-arm.txt
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Tighten operand checking on memory barrier instructions.
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2011-08-09 23:25:42 +00:00 |
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invalid-IT-CBNZ-thumb.txt
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Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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2011-09-08 22:42:49 +00:00 |
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invalid-IT-CC15.txt
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Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
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2012-03-01 22:13:02 +00:00 |
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invalid-IT-thumb.txt
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Add a testcase for r138625.
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2011-08-26 06:45:08 +00:00 |
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invalid-LDC-form-arm.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-LDM-thumb.txt
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LDM writeback is not allowed if Rn is in the target register list.
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2011-09-09 23:13:33 +00:00 |
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invalid-LDR_POST-arm.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-LDR_PRE-arm.txt
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invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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2011-08-26 20:43:14 +00:00 |
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invalid-LDRB_POST-arm.txt
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Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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2011-08-17 17:44:15 +00:00 |
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invalid-LDRD_PRE-thumb.txt
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Thumb2 assembly parsing and encoding for LDRD(immediate).
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2011-09-08 22:07:06 +00:00 |
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invalid-LDRrs-arm.txt
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Fix single word and unsigned byte data transfer instruction encodings so that
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2011-03-31 19:28:35 +00:00 |
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invalid-MCR-arm.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-MOVr-arm.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-MOVs-arm.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-MOVs-LSL-arm.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-MOVTi16-arm.txt
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Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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2011-08-10 00:03:03 +00:00 |
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invalid-MRRC2-arm.txt
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Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
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2012-04-18 13:12:50 +00:00 |
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invalid-MSRi-arm.txt
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Continue to tighten decoding by performing more operand validation.
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2011-08-11 20:21:46 +00:00 |
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invalid-RFEorLDMIA-arm.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-SBFX-arm.txt
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Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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2011-08-10 00:03:03 +00:00 |
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invalid-SMLAD-arm.txt
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Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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2011-08-10 00:03:03 +00:00 |
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invalid-SRS-arm.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-STMIA_UPD-thumb.txt
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Continue to tighten decoding by performing more operand validation.
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2011-08-11 20:21:46 +00:00 |
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invalid-SXTB-arm.txt
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Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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2011-08-10 00:03:03 +00:00 |
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invalid-t2Bcc-thumb.txt
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Tighten operand checking on memory barrier instructions.
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2011-08-09 23:25:42 +00:00 |
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invalid-t2LDRBT-thumb.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-t2LDREXD-thumb.txt
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Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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2011-09-07 19:42:28 +00:00 |
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invalid-t2LDRSHi8-thumb.txt
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Improve operand validation for Thumb2 addressing modes.
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2011-08-11 20:40:40 +00:00 |
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invalid-t2LDRSHi12-thumb.txt
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Improve operand validation for Thumb2 addressing modes.
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2011-08-11 20:40:40 +00:00 |
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invalid-t2PUSH-thumb.txt
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Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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2011-09-12 21:28:46 +00:00 |
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invalid-t2STR_POST-thumb.txt
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Improve operand validation for Thumb2 addressing modes.
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2011-08-11 20:40:40 +00:00 |
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invalid-t2STRD_PRE-thumb.txt
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Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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2011-09-07 19:42:28 +00:00 |
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invalid-t2STREXB-thumb.txt
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Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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2011-09-07 19:42:28 +00:00 |
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invalid-t2STREXD-thumb.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-UMAAL-arm.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-VLD1DUPq8_UPD-arm.txt
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Specify cpu to unbreak tests.
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2012-04-26 01:38:10 +00:00 |
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invalid-VLD3DUPd32_UPD-thumb.txt
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Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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2011-08-09 20:55:18 +00:00 |
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invalid-VLDMSDB_UPD-arm.txt
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Improve error checking in the new ARM disassembler. Patch by James Molloy.
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2011-08-11 18:24:51 +00:00 |
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invalid-VQADD-arm.txt
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Specify cpu to unbreak tests.
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2012-04-26 01:38:10 +00:00 |
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invalid-VST1d8Twb_register-thumb.txt
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Fixed a case of ARM disassembly getting an assert on a bad encoding
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2012-04-11 22:40:17 +00:00 |
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invalid-VST2b32_UPD-arm.txt
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Specify cpu to unbreak tests.
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2012-04-26 01:38:10 +00:00 |
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ldrd-armv4.txt
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Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.
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2012-04-02 15:20:39 +00:00 |
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lit.local.cfg
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Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
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2012-03-25 09:02:19 +00:00 |
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memory-arm-instructions.txt
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Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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2011-08-15 20:51:32 +00:00 |
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neon-tests.txt
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Specify cpu to unbreak tests.
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2012-04-26 01:38:10 +00:00 |
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neon.txt
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Specify cpu to unbreak tests.
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2012-04-26 01:38:10 +00:00 |
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neont2.txt
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Specify cpu to unbreak tests.
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2012-04-26 01:38:10 +00:00 |
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thumb1.txt
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Correct decoder for T1 conditional B encoding
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2012-06-06 09:12:53 +00:00 |
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thumb2.txt
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Specify cpu to unbreak tests.
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2012-04-26 01:38:10 +00:00 |
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thumb-MSR-MClass.txt
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Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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2011-09-28 14:21:38 +00:00 |
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thumb-printf.txt
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Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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2011-09-07 19:42:28 +00:00 |
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thumb-tests.txt
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Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
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2012-05-03 22:41:56 +00:00 |
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unpredictable-ADC-arm.txt
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Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
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2012-04-05 16:19:29 +00:00 |
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unpredictable-ADDREXT3-arm.txt
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Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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2012-03-22 14:14:49 +00:00 |
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unpredictable-AExtI-arm.txt
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Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
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2012-05-11 09:28:27 +00:00 |
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unpredictable-AI1cmp-arm.txt
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Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
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2012-04-18 12:48:43 +00:00 |
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unpredictable-LDR-arm.txt
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Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
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2012-03-22 13:24:43 +00:00 |
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unpredictable-LDRD-arm.txt
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Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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2012-03-22 14:14:49 +00:00 |
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unpredictable-LSL-regform.txt
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The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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2012-03-20 15:54:56 +00:00 |
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unpredictable-MRRC2-arm.txt
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Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
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2012-04-18 13:12:50 +00:00 |
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unpredictable-MRS-arm.txt
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Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
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2012-04-18 14:09:07 +00:00 |
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unpredictable-MUL-arm.txt
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Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
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2012-03-22 13:14:39 +00:00 |
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unpredictable-RSC-arm.txt
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The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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2012-03-20 15:54:56 +00:00 |
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unpredictable-SEL-arm.txt
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Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
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2012-05-11 09:28:27 +00:00 |
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unpredictable-SHADD16-arm.txt
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Added support for handling unpredictable arithmetic instructions on ARM.
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2012-04-05 16:13:15 +00:00 |
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unpredictable-SSAT-arm.txt
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The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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2012-03-20 15:54:56 +00:00 |
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unpredictable-STRBrs-arm.txt
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The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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2012-03-20 15:54:56 +00:00 |
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unpredictable-swp-arm.txt
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Added support for disassembling unpredictable swp/swpb ARM instructions.
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2012-04-18 14:18:57 +00:00 |
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unpredictable-UQADD8-arm.txt
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The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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2012-03-20 15:54:56 +00:00 |
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unpredictables-thumb.txt
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Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
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2012-02-09 10:56:31 +00:00 |
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vfp4.txt
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Fix a number of problems with ARM fused multiply add/subtract instructions.
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2012-04-11 00:13:00 +00:00 |
