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https://github.com/RPCS3/llvm-mirror.git
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ce61543897
The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
43 lines
1.3 KiB
CMake
43 lines
1.3 KiB
CMake
set(LLVM_TARGET_DEFINITIONS PPC.td)
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tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM PPCGenCodeEmitter.inc -gen-emitter)
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tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
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tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
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tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
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add_public_tablegen_target(PowerPCCommonTableGen)
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add_llvm_target(PowerPCCodeGen
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PPCAsmPrinter.cpp
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PPCBranchSelector.cpp
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PPCCodeEmitter.cpp
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PPCCTRLoops.cpp
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PPCHazardRecognizers.cpp
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PPCInstrInfo.cpp
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PPCISelDAGToDAG.cpp
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PPCISelLowering.cpp
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PPCFastISel.cpp
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PPCFrameLowering.cpp
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PPCJITInfo.cpp
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PPCMCInstLower.cpp
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PPCMachineFunctionInfo.cpp
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PPCRegisterInfo.cpp
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PPCSubtarget.cpp
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PPCTargetMachine.cpp
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PPCTargetObjectFile.cpp
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PPCTargetTransformInfo.cpp
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PPCSelectionDAGInfo.cpp
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)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(InstPrinter)
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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