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https://github.com/RPCS3/llvm-mirror.git
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702277f07f
Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
81 lines
4.7 KiB
LLVM
81 lines
4.7 KiB
LLVM
; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s
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; CHECK: vmem
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target triple = "hexagon"
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@vecpreds = external global [15 x <16 x i32>], align 64
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@vectors = external global [15 x <16 x i32>], align 64
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@vector_pairs = external global [15 x <32 x i32>], align 128
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@.str1 = external hidden unnamed_addr constant [20 x i8], align 1
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@.str2 = external hidden unnamed_addr constant [43 x i8], align 1
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@Q6VecPredResult = external global <16 x i32>, align 64
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@.str52 = external hidden unnamed_addr constant [57 x i8], align 1
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@.str54 = external hidden unnamed_addr constant [59 x i8], align 1
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@VectorResult = external global <16 x i32>, align 64
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@.str243 = external hidden unnamed_addr constant [60 x i8], align 1
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@.str251 = external hidden unnamed_addr constant [77 x i8], align 1
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@.str290 = external hidden unnamed_addr constant [65 x i8], align 1
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@VectorPairResult = external global <32 x i32>, align 128
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; Function Attrs: nounwind
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declare void @print_vector(i32, i8*) #0
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; Function Attrs: nounwind
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declare i32 @printf(i8*, ...) #0
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; Function Attrs: nounwind
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declare void @print_vecpred(i32, i8*) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1
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; Function Attrs: nounwind
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declare void @init_vectors() #0
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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; Function Attrs: nounwind
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declare void @init_addresses() #0
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; Function Attrs: nounwind
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declare <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 0), align 64
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%1 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64
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call void @print_vecpred(i32 64, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*))
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%2 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64
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%call50 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([57 x i8], [57 x i8]* @.str52, i32 0, i32 0)) #3
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%3 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64
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%call52 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @.str54, i32 0, i32 0)) #3
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%4 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64
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%call300 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([65 x i8], [65 x i8]* @.str290, i32 0, i32 0)) #3
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%5 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 0), align 64
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%6 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64
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%call1373 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([20 x i8], [20 x i8]* @.str1, i32 0, i32 0), i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str2, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @.str243, i32 0, i32 0)) #3
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%7 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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%call1381 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([20 x i8], [20 x i8]* @.str1, i32 0, i32 0), i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str2, i32 0, i32 0), i8* getelementptr inbounds ([77 x i8], [77 x i8]* @.str251, i32 0, i32 0)) #3
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%8 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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%9 = call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %8, i32 16843009)
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call void @print_vector(i32 64, i8* bitcast (<16 x i32>* @VectorResult to i8*))
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%10 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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%11 = call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %10, i32 16843009)
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%12 = bitcast <512 x i1> %11 to <16 x i32>
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%13 = bitcast <16 x i32> %12 to <512 x i1>
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%14 = call <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1> %13, <16 x i32> undef, <16 x i32> undef)
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store <16 x i32> %14, <16 x i32>* @VectorResult, align 64
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ret i32 0
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #3 = { nounwind }
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