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c4d75790e7
Previously, we marked the branch conditions of latch blocks uniform after vectorization if they were instructions contained in the loop. However, if a condition instruction has users other than the branch, it may not remain uniform. This patch ensures the conditions we mark uniform are only used by the branch. This should fix PR30627. Reference: https://llvm.org/bugs/show_bug.cgi?id=30627 llvm-svn: 283563
36 lines
1.2 KiB
LLVM
36 lines
1.2 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -instcombine -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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; CHECK-LABEL: more_than_one_use
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;
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; PR30627. Check that a compare instruction with more than one use is not
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; recognized as uniform and is vectorized.
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;
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; CHECK-NOT: Found uniform instruction: %cond = icmp slt i64 %i.next, %n
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; CHECK: vector.body
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; CHECK: %[[I:.+]] = add nuw nsw <4 x i64> %vec.ind, <i64 1, i64 1, i64 1, i64 1>
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; CHECK: icmp slt <4 x i64> %[[I]], %broadcast.splat
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; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
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;
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define i32 @more_than_one_use(i32* %a, i64 %n) {
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
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%r = phi i32 [ %tmp3, %for.body ], [ 0, %entry ]
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%i.next = add nuw nsw i64 %i, 1
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%cond = icmp slt i64 %i.next, %n
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%tmp0 = select i1 %cond, i64 %i.next, i64 0
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%tmp1 = getelementptr inbounds i32, i32* %a, i64 %tmp0
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%tmp2 = load i32, i32* %tmp1, align 8
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%tmp3 = add i32 %r, %tmp2
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br i1 %cond, label %for.body, label %for.end
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for.end:
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%tmp4 = phi i32 [ %tmp3, %for.body ]
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ret i32 %tmp4
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}
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