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22e87bbb08
Having an enum member named Default is quite confusing: Is it distinct from the others? This patch removes that member and instead uses Optional<Reloc> in places where we have a user input that still hasn't been maped to the default value, which is now clear has no be one of the remaining 3 options. llvm-svn: 269988
86 lines
2.7 KiB
C++
86 lines
2.7 KiB
C++
//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETMACHINE_H
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#define LLVM_LIB_TARGET_POWERPC_PPCTARGETMACHINE_H
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#include "PPCInstrInfo.h"
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#include "PPCSubtarget.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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/// Common code between 32-bit and 64-bit PowerPC targets.
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///
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class PPCTargetMachine : public LLVMTargetMachine {
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public:
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enum PPCABI { PPC_ABI_UNKNOWN, PPC_ABI_ELFv1, PPC_ABI_ELFv2 };
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private:
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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PPCABI TargetABI;
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PPCSubtarget Subtarget;
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mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
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public:
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PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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~PPCTargetMachine() override;
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const PPCSubtarget *getSubtargetImpl(const Function &F) const override;
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetIRAnalysis getTargetIRAnalysis() override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
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bool isPPC64() const {
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const Triple &TT = getTargetTriple();
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return (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
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};
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};
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/// PowerPC 32-bit target machine.
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///
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class PPC32TargetMachine : public PPCTargetMachine {
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virtual void anchor();
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public:
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PPC32TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// PowerPC 64-bit target machine.
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///
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class PPC64TargetMachine : public PPCTargetMachine {
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virtual void anchor();
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public:
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PPC64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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