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f035685176
llvm-mirror/test/CodeGen
History
Chris Lattner f035685176 down with unwind info :) 
llvm-svn: 74206
2009-06-25 21:48:17 +00:00
..
Alpha
ARM ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 2009-06-25 20:59:23 +00:00
CBackend Fix an erroneous check for isFNeg; the FNeg case is handled 2009-06-04 23:43:29 +00:00
CellSPU Add some generic expansion logic for SMULO and UMULO. Fixes UMULO 2009-06-16 06:58:29 +00:00
CPP
Generic Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
IA64
Mips Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
MSP430 Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
PowerPC Add some generic expansion logic for SMULO and UMULO. Fixes UMULO 2009-06-16 06:58:29 +00:00
SPARC Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
Thumb We should run these tests as well. 2009-06-24 21:36:26 +00:00
Thumb2 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 2009-06-25 20:59:23 +00:00
X86 down with unwind info :) 2009-06-25 21:48:17 +00:00
XCore Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00