Simon Pilgrim f0a2f7f0f9 [CostModel][X86] Adjust fp<->int vXi32 SSE legalized costs based on llvm-mca reports. ... Building on rG2a1ef8784ad9a, adjust the SSE cost tables to use the legalized types based on the worst case costs from the script in D103695. To account for different numbers of src/dst legalized type registers we must scale the cost by maximum of the src/dst, not just use src		2021-07-01 15:34:20 +01:00
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AArch64	[CostModel][AArch64] Improve cost model for vector reduction intrinsics	2021-06-24 12:02:58 +01:00
AMDGPU	[AMDGPU] PHI node cost should not be counted for the size and latency.	2021-06-30 16:11:17 +03:00
ARM	[InstructionCost] Don't conflate Invalid costs with Unknown costs.	2021-03-30 09:29:42 +01:00
PowerPC	[Cost]Canonicalize the cost for logical or/and reductions.	2021-03-19 11:01:58 -07:00
RISCV	[RISCV] Expand unaligned fixed-length vector memory accesses	2021-06-02 09:27:44 +01:00
SystemZ	Revert "[NFC] remove explicit default value for strboolattr attribute in tests"	2021-05-24 19:43:40 +02:00
X86	[CostModel][X86] Adjust fp<->int vXi32 SSE legalized costs based on llvm-mca reports.	2021-07-01 15:34:20 +01:00
free-intrinsics-datalayout.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
free-intrinsics-no_info.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
no_info.ll