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49cca90a3f
Summary: The addr64-based legalization is incorrect for MUBUF instructions with idxen set as well as for BUFFER_LOAD/STORE_FORMAT_* instructions. This affects e.g. shaders that access buffer textures. Since we never actually need the addr64-legalization in shaders, this patch takes the easy route and keys off the calling convention. If this ever affects (non-OpenGL) compute, the type of legalization needs to be chosen based on some TSFlag. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98664 Reviewers: arsenm, tstellarAMD Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D26747 llvm-svn: 287339
50 lines
2.2 KiB
LLVM
50 lines
2.2 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
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; Test that buffer_load_format with VGPR resource descriptor is properly
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; legalized.
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; CHECK-LABEL: {{^}}test_none:
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; CHECK: buffer_load_format_x v0, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define amdgpu_vs float @test_none(<4 x i32> addrspace(2)* inreg %base, i32 %i) {
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main_body:
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%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %base, i32 %i
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%tmp2 = load <4 x i32>, <4 x i32> addrspace(2)* %ptr, align 32
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%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 0, i1 0, i1 0)
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ret float %tmp7
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}
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; CHECK-LABEL: {{^}}test_idxen:
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; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen{{$}}
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define amdgpu_vs float @test_idxen(<4 x i32> addrspace(2)* inreg %base, i32 %i) {
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main_body:
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%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %base, i32 %i
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%tmp2 = load <4 x i32>, <4 x i32> addrspace(2)* %ptr, align 32
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%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i1 0, i1 0)
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ret float %tmp7
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}
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; CHECK-LABEL: {{^}}test_offen:
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; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
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define amdgpu_vs float @test_offen(<4 x i32> addrspace(2)* inreg %base, i32 %i) {
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main_body:
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%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %base, i32 %i
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%tmp2 = load <4 x i32>, <4 x i32> addrspace(2)* %ptr, align 32
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%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 undef, i1 0, i1 0)
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ret float %tmp7
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}
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; CHECK-LABEL: {{^}}test_both:
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; CHECK: buffer_load_format_x v0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen{{$}}
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define amdgpu_vs float @test_both(<4 x i32> addrspace(2)* inreg %base, i32 %i) {
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main_body:
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%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %base, i32 %i
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%tmp2 = load <4 x i32>, <4 x i32> addrspace(2)* %ptr, align 32
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%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 undef, i1 0, i1 0)
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ret float %tmp7
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}
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declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) nounwind readonly
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attributes #0 = { nounwind readnone }
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