mirror of
https://github.com/RPCS3/llvm-mirror.git
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d773f533b9
Summary: GCNSchedStrategy re-uses most of GenericScheduler, it's just uses a different method to compute the excess and critical register pressure limits. It's not enabled by default, to enable it you need to pass -misched=gcn to llc. Shader DB stats: 32464 shaders in 17874 tests Totals: SGPRS: 1542846 -> 1643125 (6.50 %) VGPRS: 1005595 -> 904653 (-10.04 %) Spilled SGPRs: 29929 -> 27745 (-7.30 %) Spilled VGPRs: 334 -> 352 (5.39 %) Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread Code Size: 36688188 -> 37034900 (0.95 %) bytes LDS: 1913 -> 1913 (0.00 %) blocks Max Waves: 254101 -> 265125 (4.34 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 1338220 -> 1438499 (7.49 %) VGPRS: 886221 -> 785279 (-11.39 %) Spilled SGPRs: 29869 -> 27685 (-7.31 %) Spilled VGPRs: 334 -> 352 (5.39 %) Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread Code Size: 34315716 -> 34662428 (1.01 %) bytes LDS: 1551 -> 1551 (0.00 %) blocks Max Waves: 188127 -> 199151 (5.86 %) Wait states: 0 -> 0 (0.00 %) Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrick Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: https://reviews.llvm.org/D23688 llvm-svn: 279995
129 lines
4.3 KiB
LLVM
129 lines
4.3 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}rcp_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%rcp = fdiv float 1.0, %src
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_ulp25_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_ulp25_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%rcp = fdiv float 1.0, %src, !fpmath !0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_fast_ulp25_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_fast_ulp25_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%rcp = fdiv fast float 1.0, %src, !fpmath !0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_arcp_ulp25_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_arcp_ulp25_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%rcp = fdiv arcp float 1.0, %src, !fpmath !0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_global_fast_ulp25_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_global_fast_ulp25_pat_f32(float addrspace(1)* %out, float %src) #2 {
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%rcp = fdiv float 1.0, %src, !fpmath !0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_fabs_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], |[[SRC]]|
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_fabs_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%src.fabs = call float @llvm.fabs.f32(float %src)
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%rcp = fdiv float 1.0, %src.fabs
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}neg_rcp_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -[[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @neg_rcp_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%rcp = fdiv float -1.0, %src
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_fabs_fneg_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -|[[SRC]]|
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; GCN: buffer_store_dword [[RCP]]
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define void @rcp_fabs_fneg_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%src.fabs = call float @llvm.fabs.f32(float %src)
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%src.fabs.fneg = fsub float -0.0, %src.fabs
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%rcp = fdiv float 1.0, %src.fabs.fneg
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_fabs_fneg_pat_multi_use_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -|[[SRC]]|
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; GCN: v_mul_f32_e64 [[MUL:v[0-9]+]], [[SRC]], -|[[SRC]]|
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; GCN: buffer_store_dword [[RCP]]
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; GCN: buffer_store_dword [[MUL]]
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define void @rcp_fabs_fneg_pat_multi_use_f32(float addrspace(1)* %out, float %src) #0 {
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%src.fabs = call float @llvm.fabs.f32(float %src)
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%src.fabs.fneg = fsub float -0.0, %src.fabs
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%rcp = fdiv float 1.0, %src.fabs.fneg
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store volatile float %rcp, float addrspace(1)* %out, align 4
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%other = fmul float %src, %src.fabs.fneg
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store volatile float %other, float addrspace(1)* %out, align 4
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ret void
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}
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declare float @llvm.fabs.f32(float) #1
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declare float @llvm.sqrt.f32(float) #1
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attributes #0 = { nounwind "unsafe-fp-math"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "unsafe-fp-math"="true" }
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!0 = !{float 2.500000e+00}
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