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cd4ff3e8fc
output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
76 lines
1.7 KiB
YAML
76 lines
1.7 KiB
YAML
# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumb-none--eabi"
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define i32 @f(i32 %a, i32 %b) {
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entry:
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%mul = mul nsw i32 %b, %a
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%cmp = icmp eq i32 %mul, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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...
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---
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name: f
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# CHECK-LABEL: name: f
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: tgpr }
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- { id: 1, class: tgpr }
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- { id: 2, class: tgpr }
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- { id: 3, class: tgpr }
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- { id: 4, class: tgpr }
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- { id: 5, class: tgpr }
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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- { reg: '%r1', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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# CHECK: tMOVi8 1, 14, %noreg
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# CHECK: tMOVi8 0, 14, %noreg
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# CHECK: tMUL %1, %0, 14, %noreg
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# CHECK-NOT: tCMPi8
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body: |
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bb.0.entry:
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liveins: %r0, %r1
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%1 = COPY %r1
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%0 = COPY %r0
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%2, %cpsr = tMUL %1, %0, 14, %noreg
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%3, %cpsr = tMOVi8 1, 14, %noreg
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%4, %cpsr = tMOVi8 0, 14, %noreg
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tCMPi8 killed %2, 0, 14, %noreg, implicit-def %cpsr
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tBcc %bb.2.entry, 0, %cpsr
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bb.1.entry:
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bb.2.entry:
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%5 = PHI %4, %bb.1.entry, %3, %bb.0.entry
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%r0 = COPY %5
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tBX_RET 14, %noreg, implicit %r0
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...
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