Artem Tamazov f16982e6bd [AMDGPU][llvm-mc] Quickfix for r272748 to enable labels in branch instructions. ... Fixes issue mentioned at: https://github.com/RadeonOpenCompute/LLVM-AMDGPU-Assembler-Extra/issues/13. Lit tests added. Differential Revision: http://reviews.llvm.org/D22133 llvm-svn: 275054		2016-07-11 12:07:18 +00:00
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AArch64	AArch64: TableGenerate system instruction operands.	2016-07-05 21:23:04 +00:00
AMDGPU	[AMDGPU][llvm-mc] Quickfix for r272748 to enable labels in branch instructions.	2016-07-11 12:07:18 +00:00
ARM	[ARM] Accept conditional versions of BXNS and BLXNS	2016-06-07 14:58:48 +00:00
AsmParser	Refactor and cleanup Assembly Parsing / Lexing	2016-06-17 16:06:17 +00:00
COFF	[MC, COFF] Permit a variable to be redefined	2016-07-08 21:54:16 +00:00
Disassembler	[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support	2016-07-11 07:41:56 +00:00
ELF	Add initial support for R_386_GOT32X.	2016-07-06 21:19:11 +00:00
Hexagon	Remove redundant -mattr options from llvm-objdump commands.	2016-06-16 15:47:19 +00:00
Lanai	[lanai] Treat .t as optional in assembly parser for RR operands and add predicate operand to ShiftRR	2016-07-09 18:26:04 +00:00
MachO	CodeGen: Use PLT relocations for relative references to unnamed_addr functions.	2016-04-22 20:40:10 +00:00
Markup
Mips	[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support	2016-07-11 07:41:56 +00:00
PowerPC	Add aliases for mfvrsave/mtvrsave.	2016-06-09 23:27:48 +00:00
Sparc	Don't pass a Reloc::Model to MC.	2016-05-18 11:58:50 +00:00
SystemZ	[SystemZ] Add support for the .word directive.	2016-07-08 16:50:02 +00:00
X86	Permit memory operands in ins/outs instructions	2016-06-29 19:54:27 +00:00