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5efe040582
Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
180 lines
7.9 KiB
LLVM
180 lines
7.9 KiB
LLVM
; Disable machine cse to stress the different path of the algorithm.
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; Otherwise, we always fall in the simple case, i.e., only one definition.
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; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-stress-promote-const -mcpu=cyclone | FileCheck -check-prefix=PROMOTED %s
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; The REGULAR run just checks that the inputs passed to promote const expose
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; the appropriate patterns.
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; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-enable-promote-const=false -mcpu=cyclone | FileCheck -check-prefix=REGULAR %s
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%struct.uint8x16x4_t = type { [4 x <16 x i8>] }
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; Constant is a structure
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define %struct.uint8x16x4_t @test1() {
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; PROMOTED-LABEL: test1:
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; Promote constant has created a big constant for the whole structure
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; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], __PromotedConst@PAGE
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; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], __PromotedConst@PAGEOFF
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; Destination registers are defined by the ABI
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; PROMOTED-NEXT: ldp q0, q1, {{\[}}[[BASEADDR]]]
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; PROMOTED-NEXT: ldp q2, q3, {{\[}}[[BASEADDR]], #32]
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; PROMOTED-NEXT: ret
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; REGULAR-LABEL: test1:
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; Regular access is quite bad, it performs 4 loads, one for each chunk of
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; the structure
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; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
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; Destination registers are defined by the ABI
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; REGULAR: ldr q0, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
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; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
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; REGULAR: ldr q1, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
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; REGULAR: adrp [[PAGEADDR2:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE
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; REGULAR: ldr q2, {{\[}}[[PAGEADDR2]], [[CSTLABEL2]]@PAGEOFF]
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; REGULAR: adrp [[PAGEADDR3:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE
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; REGULAR: ldr q3, {{\[}}[[PAGEADDR3]], [[CSTLABEL3]]@PAGEOFF]
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; REGULAR-NEXT: ret
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entry:
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ret %struct.uint8x16x4_t { [4 x <16 x i8>] [<16 x i8> <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, <16 x i8> <i8 32, i8 124, i8 121, i8 120, i8 8, i8 117, i8 -56, i8 113, i8 -76, i8 110, i8 -53, i8 107, i8 7, i8 105, i8 103, i8 102>, <16 x i8> <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>, <16 x i8> <i8 -104, i8 83, i8 -20, i8 81, i8 81, i8 80, i8 -59, i8 78, i8 73, i8 77, i8 -37, i8 75, i8 122, i8 74, i8 37, i8 73>] }
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}
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; Two different uses of the same constant in the same basic block
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define <16 x i8> @test2(<16 x i8> %arg) {
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entry:
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; PROMOTED-LABEL: test2:
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; In stress mode, constant vector are promoted
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; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst.[0-9]+]]@PAGE
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; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
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; Destination register is defined by ABI
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; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
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; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]]
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; PROMOTED-NEXT: ret
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; REGULAR-LABEL: test2:
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; Regular access is strickly the same as promoted access.
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; The difference is that the address (and thus the space in memory) is not
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; shared between constants
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; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
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; REGULAR: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
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; Destination register is defined by ABI
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; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
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; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]]
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; REGULAR-NEXT: ret
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%add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
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%mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
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%add.i9 = add <16 x i8> %add.i, %mul.i
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ret <16 x i8> %add.i9
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}
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; Two different uses of the same constant in two different basic blocks,
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; one dominates the other
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define <16 x i8> @test3(<16 x i8> %arg, i32 %path) {
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; PROMOTED-LABEL: test3:
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; In stress mode, constant vector are promoted
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; Since, the constant is the same as the previous function,
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; the same address must be used
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; PROMOTED: ldr
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; PROMOTED: ldr
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; PROMOTED-NOT: ldr
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; PROMOTED: ret
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; REGULAR-LABEL: test3:
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; REGULAR: ldr
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; REGULAR: ldr
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; REGULAR-NOT: ldr
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; REGULAR: ret
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entry:
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%add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
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%tobool = icmp eq i32 %path, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%mul.i13 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
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br label %if.end
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if.else: ; preds = %entry
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%mul.i = mul <16 x i8> %add.i, <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%ret2.0 = phi <16 x i8> [ %mul.i13, %if.then ], [ %mul.i, %if.else ]
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%add.i12 = add <16 x i8> %add.i, %ret2.0
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ret <16 x i8> %add.i12
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}
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; Two different uses of the sane constant in two different basic blocks,
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; none dominates the other
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define <16 x i8> @test4(<16 x i8> %arg, i32 %path) {
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; PROMOTED-LABEL: test4:
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; In stress mode, constant vector are promoted
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; Since, the constant is the same as the previous function,
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; the same address must be used
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; PROMOTED: ldr
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; PROMOTED-NOT: ldr
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; PROMOTED: ret
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; REGULAR-LABEL: test4:
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; REGULAR: ldr
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; REGULAR-NOT: ldr
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; REGULAR: ret
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entry:
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%add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
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%tobool = icmp eq i32 %path, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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%mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
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br label %if.end
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if.end: ; preds = %entry, %if.then
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%ret.0 = phi <16 x i8> [ %mul.i, %if.then ], [ %add.i, %entry ]
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ret <16 x i8> %ret.0
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}
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; Two different uses of the sane constant in two different basic blocks,
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; one is in a phi.
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define <16 x i8> @test5(<16 x i8> %arg, i32 %path) {
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; PROMOTED-LABEL: test5:
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; In stress mode, constant vector are promoted
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; Since, the constant is the same as the previous function,
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; the same address must be used
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; PROMOTED: ldr
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; PROMOTED-NOT: ldr
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; PROMOTED: ret
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; REGULAR-LABEL: test5:
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; REGULAR: ldr
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; REGULAR: ret
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entry:
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%tobool = icmp eq i32 %path, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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%add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
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%mul.i26 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
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br label %if.end
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if.end: ; preds = %entry, %if.then
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%ret.0 = phi <16 x i8> [ %mul.i26, %if.then ], [ <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, %entry ]
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%mul.i25 = mul <16 x i8> %ret.0, %ret.0
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%mul.i24 = mul <16 x i8> %mul.i25, %mul.i25
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%mul.i23 = mul <16 x i8> %mul.i24, %mul.i24
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%mul.i = mul <16 x i8> %mul.i23, %mul.i23
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ret <16 x i8> %mul.i
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}
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define void @accessBig(i64* %storage) {
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; PROMOTED-LABEL: accessBig:
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; PROMOTED: adrp
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; PROMOTED: ret
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%addr = bitcast i64* %storage to <1 x i80>*
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store <1 x i80> <i80 483673642326615442599424>, <1 x i80>* %addr
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ret void
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}
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define void @asmStatement() {
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; PROMOTED-LABEL: asmStatement:
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; PROMOTED-NOT: adrp
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; PROMOTED: ret
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call void asm sideeffect "bfxil w0, w0, $0, $1", "i,i"(i32 28, i32 4)
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ret void
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}
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