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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 04:52:54 +02:00
llvm-mirror/test/MC/COFF
Jonas Devlieghere 9550ad611d [CodeView] Add prefix to CodeView registers.
Adds CVReg to CodeView register names to prevent a duplicate symbol with
CR3 defined in termios.h, as suggested by Zachary on the mailing list.

http://lists.llvm.org/pipermail/llvm-dev/2018-May/123372.html

Differential revision: https://reviews.llvm.org/D47478

rdar://39863705

llvm-svn: 333421
2018-05-29 14:35:34 +00:00
..
ARM
alias.s
align-nops.s [X86] Don't use NOPL when the assembler is passed an empty CPU string. Update tests to force a CPU with NOPL 2017-12-18 21:37:27 +00:00
bad-expr.s
basic-coff-64.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
basic-coff.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bigobj.py
bss_section.ll
bss.s
comm-align.s
comm.ll
comm.s
const-gv-with-rel-init.ll
cross-section-relative-err.s
cross-section-relative.ll
cross-section-relative.s
cv-compiler-info.ll [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
cv-def-range-gap.s [CodeView] Add prefix to CodeView registers. 2018-05-29 14:35:34 +00:00
cv-def-range.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
cv-empty-file-table.s
cv-empty-linetable.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
cv-errors.s
cv-fpo-csrs.s [codeview] Implement FPO data assembler directives 2017-10-11 21:24:33 +00:00
cv-fpo-errors.s [codeview] Implement FPO data assembler directives 2017-10-11 21:24:33 +00:00
cv-fpo-setframe.s [codeview] Implement FPO data assembler directives 2017-10-11 21:24:33 +00:00
cv-inline-linetable-infloop.s
cv-inline-linetable-unlikely.s
cv-inline-linetable-unreachable.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
cv-inline-linetable.s [CodeView] Add line numbers for inlined call sites 2018-01-18 22:55:43 +00:00
cv-loc-cross-section.s
cv-loc-unreachable.s [codeview] Ignore .cv_loc directives at the end of a function 2018-04-25 23:34:15 +00:00
cv-loc.s
diff.s [MC] Always emit relocations for same-section function references 2018-03-14 19:24:32 +00:00
directive-section-characteristics.ll
early-dce.s
eh-frame.s
feat00.s
file.s
global_ctors_dtors.ll
initialised-data.ll
invalid-def.s
invalid-endef.s
invalid-scl-range.s
invalid-scl.s
invalid-type-range.s
invalid-type.s
ir-to-imgrel.ll
label-undefined.s
linker-options.ll
linkonce-invalid.s
linkonce.s
lit.local.cfg
lset0.s
module-asm.ll
offset.s
pr23025.s
pr28462.s
rdata.ll
relax-reloc.s
relocation-imgrel.s
safeseh.s
secidx.s
secrel32-undef.s
secrel32.s
secrel-variant.s
section-comdat-conflict2.s
section-comdat-conflict.s
section-comdat.s
section-invalid-flags.s
section-name-encoding.s
section-passthru-flags.s
section.s
seh-align1.s
seh-align2.s
seh-align3.s
seh-linkonce.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
seh-section-2.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
seh-section.s
seh-stackalloc-zero.s
seh.s
simple-fixups.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
stdin.s
switch-relocations.ll
symbol-alias.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
symbol-fragment-offset-64.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
symbol-fragment-offset.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
symidx.s Reland "Emit Function IDs table for Control Flow Guard" 2018-01-09 23:49:30 +00:00
temporary-alias.s
timestamp.s
tricky-names.ll MC intel asm parser: Allow @ at the start of function names. 2018-03-12 12:47:27 +00:00
weak-alias-local.s
weak-val.s
weak.s [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00