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f1f355c706
pushl %ebp movl %esp, %ebp movl $42, %eax popl %ebp ret llvm-svn: 95344
227 lines
6.3 KiB
C++
227 lines
6.3 KiB
C++
//===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86MCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "x86-emitter"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class X86MCCodeEmitter : public MCCodeEmitter {
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X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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public:
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X86MCCodeEmitter(TargetMachine &tm)
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: TM(tm), TII(*TM.getInstrInfo()) {
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}
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~X86MCCodeEmitter() {}
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static unsigned GetX86RegNum(const MCOperand &MO) {
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return X86RegisterInfo::getX86RegNum(MO.getReg());
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}
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void EmitByte(unsigned char C, raw_ostream &OS) const {
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OS << (char)C;
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}
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void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
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// Output the constant in little endian byte order.
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for (unsigned i = 0; i != Size; ++i) {
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EmitByte(Val & 255, OS);
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Val >>= 8;
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}
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}
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
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raw_ostream &OS) const {
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EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), OS);
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}
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createX86MCCodeEmitter(const Target &,
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TargetMachine &TM) {
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return new X86MCCodeEmitter(TM);
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}
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void X86MCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = TII.get(Opcode);
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unsigned TSFlags = Desc.TSFlags;
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// FIXME: We should emit the prefixes in exactly the same order as GAS does,
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// in order to provide diffability.
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// Emit the lock opcode prefix as needed.
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if (TSFlags & X86II::LOCK)
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EmitByte(0xF0, OS);
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// Emit segment override opcode prefix as needed.
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switch (TSFlags & X86II::SegOvrMask) {
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default: assert(0 && "Invalid segment!");
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case 0: break; // No segment override!
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case X86II::FS:
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EmitByte(0x64, OS);
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break;
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case X86II::GS:
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EmitByte(0x65, OS);
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break;
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}
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// Emit the repeat opcode prefix as needed.
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if ((TSFlags & X86II::Op0Mask) == X86II::REP)
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EmitByte(0xF3, OS);
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// Emit the operand size opcode prefix as needed.
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if (TSFlags & X86II::OpSize)
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EmitByte(0x66, OS);
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// Emit the address size opcode prefix as needed.
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if (TSFlags & X86II::AdSize)
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EmitByte(0x67, OS);
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bool Need0FPrefix = false;
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switch (TSFlags & X86II::Op0Mask) {
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default: assert(0 && "Invalid prefix!");
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case 0: break; // No prefix!
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case X86II::REP: break; // already handled.
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case X86II::TB: // Two-byte opcode prefix
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case X86II::T8: // 0F 38
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case X86II::TA: // 0F 3A
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Need0FPrefix = true;
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break;
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case X86II::TF: // F2 0F 38
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EmitByte(0xF2, OS);
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Need0FPrefix = true;
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break;
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case X86II::XS: // F3 0F
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EmitByte(0xF3, OS);
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Need0FPrefix = true;
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break;
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case X86II::XD: // F2 0F
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EmitByte(0xF2, OS);
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Need0FPrefix = true;
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break;
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case X86II::D8: EmitByte(0xD8, OS); break;
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case X86II::D9: EmitByte(0xD9, OS); break;
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case X86II::DA: EmitByte(0xDA, OS); break;
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case X86II::DB: EmitByte(0xDB, OS); break;
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case X86II::DC: EmitByte(0xDC, OS); break;
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case X86II::DD: EmitByte(0xDD, OS); break;
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case X86II::DE: EmitByte(0xDE, OS); break;
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case X86II::DF: EmitByte(0xDF, OS); break;
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}
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// Handle REX prefix.
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#if 0 // FIXME: Add in, also, can this come before F2 etc to simplify emission?
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if (Is64BitMode) {
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if (unsigned REX = X86InstrInfo::determineREX(MI))
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EmitByte(0x40 | REX, OS);
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}
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#endif
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// 0x0F escape code must be emitted just before the opcode.
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if (Need0FPrefix)
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EmitByte(0x0F, OS);
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// FIXME: Pull this up into previous switch if REX can be moved earlier.
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switch (TSFlags & X86II::Op0Mask) {
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case X86II::TF: // F2 0F 38
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case X86II::T8: // 0F 38
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EmitByte(0x38, OS);
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break;
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case X86II::TA: // 0F 3A
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EmitByte(0x3A, OS);
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break;
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}
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// If this is a two-address instruction, skip one of the register operands.
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unsigned NumOps = Desc.getNumOperands();
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unsigned CurOp = 0;
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if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
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++CurOp;
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else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
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// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
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--NumOps;
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unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(Desc);
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switch (TSFlags & X86II::FormMask) {
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default: assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
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case X86II::RawFrm: {
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EmitByte(BaseOpcode, OS);
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if (CurOp == NumOps)
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break;
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assert(0 && "Unimpl RawFrm expr");
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break;
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}
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case X86II::AddRegFrm: {
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EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)),OS);
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if (CurOp == NumOps)
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break;
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const MCOperand &MO1 = MI.getOperand(CurOp++);
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if (MO1.isImm()) {
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unsigned Size = X86InstrInfo::sizeOfImm(&Desc);
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EmitConstant(MO1.getImm(), Size, OS);
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break;
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}
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assert(0 && "Unimpl AddRegFrm expr");
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break;
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}
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case X86II::MRMDestReg:
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EmitByte(BaseOpcode, OS);
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EmitRegModRMByte(MI.getOperand(CurOp),
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GetX86RegNum(MI.getOperand(CurOp+1)), OS);
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CurOp += 2;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(&Desc), OS);
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break;
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}
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#ifndef NDEBUG
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if (!Desc.isVariadic() && CurOp != NumOps) {
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errs() << "Cannot encode all operands of: ";
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MI.dump();
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errs() << '\n';
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abort();
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}
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#endif
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}
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