mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 11:02:59 +02:00
8ad04e7f1d
Revision 320791 introduced a pass that transforms reg+reg instructions to reg+imm if they're fed by "load immediate". However, it didn't handle out-of-range shifts correctly as reported in PR35688. This patch fixes that and therefore the PR. Furthermore, there was undefined behaviour in the patch where the RHS of an initialization expression was 32 bits and constant `1` was shifted left 32 bits. This was fixed by ensuring the RHS is 64 bits just like the LHS. Differential Revision: https://reviews.llvm.org/D41369 llvm-svn: 321551
35 lines
1.3 KiB
LLVM
35 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
|
|
; RUN: FileCheck %s
|
|
; Function Attrs: nounwind
|
|
define void @ec_GFp_nistp256_points_mul() {
|
|
; CHECK-LABEL: ec_GFp_nistp256_points_mul:
|
|
; CHECK: ld 5, 0(3)
|
|
; CHECK: li 3, 127
|
|
; CHECK: li 4, 0
|
|
; CHECK: subfic 6, 5, 0
|
|
; CHECK: subfze 6, 4
|
|
; CHECK: sradi 7, 6, 63
|
|
; CHECK: srad 6, 6, 3
|
|
; CHECK: subfc 5, 5, 7
|
|
; CHECK: subfe 5, 4, 6
|
|
; CHECK: sradi 5, 5, 63
|
|
entry:
|
|
br label %fe_cmovznz.exit.i534.i.15
|
|
|
|
fe_cmovznz.exit.i534.i.15: ; preds = %fe_cmovznz.exit.i534.i.15, %entry
|
|
%0 = load i64, i64* undef, align 8
|
|
%1 = load i64, i64* undef, align 8
|
|
%conv.i69.i.i = zext i64 %0 to i128
|
|
%sub.i72.i.i = sub nsw i128 0, %conv.i69.i.i
|
|
%conv.i63.i.i = zext i64 %1 to i128
|
|
%add.neg.i.i.i = ashr i128 %sub.i72.i.i, 127
|
|
%sub.i65.i.i = sub nsw i128 %add.neg.i.i.i, %conv.i63.i.i
|
|
%sub.i65.lobit.i.i = ashr i128 %sub.i65.i.i, 127
|
|
%conv1.i58.i.i = and i128 %sub.i65.lobit.i.i, 18446744073709551615
|
|
%add3.i59.i.i = add nuw nsw i128 %conv1.i58.i.i, 0
|
|
%conv4.i60.i.i = trunc i128 %add3.i59.i.i to i64
|
|
store i64 %conv4.i60.i.i, i64* undef, align 16
|
|
br label %fe_cmovznz.exit.i534.i.15
|
|
}
|