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aee5f0fc5d
- Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
32 lines
1.6 KiB
LLVM
32 lines
1.6 KiB
LLVM
; RUN: llc %s -O0 -march=sparc -mcpu=leon3 -mattr=+hasleoncasa -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=gr712rc -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=leon4 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=gr740 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=myriad2 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=myriad2.1 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=myriad2.2 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=myriad2.3 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2100 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2150 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2155 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2450 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2455 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2x5x -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2080 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2085 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2480 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2485 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=ma2x8x -o - | FileCheck %s
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; CHECK-LABEL: casa_test
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; CHECK-DAG: mov 1, [[R0:%[a-z0-9]+]]
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; CHECK-DAG: mov %g0, [[R1:%[a-z0-9]+]]
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; CHECK: casa [{{%[a-z0-9]+}}] 10, [[R1]], [[R0]]
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define void @casa_test(i32* %ptr) {
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%pair = cmpxchg i32* %ptr, i32 0, i32 1 monotonic monotonic
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%r = extractvalue { i32, i1 } %pair, 0
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%stored1 = icmp eq i32 %r, 0
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ret void
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}
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