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The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds LLVM support to enable those builtins. In partciular, the patch: - adds the transactional-execution and processor-assist facilities - adds MC support for all instructions provided by those facilities - adds LLVM intrinsics for those instructions and hooks them up for CodeGen - adds CodeGen support to optimize CC return value checking Since this is first use of target-specific intrinsics on the platform, the patch creates the include/llvm/IR/IntrinsicsSystemZ.td file and hooks it up in Intrinsics.td. I've also changed Triple::getArchTypePrefix to return "s390" instead of "systemz", since the naming convention for GCC intrinsics uses "s390" on the platform, and it neemed more straight- forward to use the same convention for LLVM IR intrinsics. An associated clang patch makes the intrinsics (and command line switches) available at the source-language level. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html Index: llvm-head/lib/Target/SystemZ/SystemZOperators.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZOperators.td +++ llvm-head/lib/Target/SystemZ/SystemZOperators.td @@ -79,6 +79,9 @@ def SDT_ZI32Intrinsic : SDTypeProf def SDT_ZPrefetch : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>; +def SDT_ZTBegin : SDTypeProfile<0, 2, + [SDTCisPtrTy<0>, + SDTCisVT<1, i32>]>; //===----------------------------------------------------------------------===// // Node definitions @@ -180,6 +183,15 @@ def z_prefetch : SDNode<"System [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin, + [SDNPHasChain, SDNPOutGlue, SDNPMayStore, + SDNPSideEffect]>; +def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin, + [SDNPHasChain, SDNPOutGlue, SDNPMayStore, + SDNPSideEffect]>; +def z_tend : SDNode<"SystemZISD::TEND", SDTNone, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; + //===----------------------------------------------------------------------===// // Pattern fragments //===----------------------------------------------------------------------===// Index: llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZInstrFormats.td +++ llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td @@ -473,6 +473,17 @@ class InstSS<bits<8> op, dag outs, dag i let Inst{15-0} = BD2; } +class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<4, outs, ins, asmstr, pattern> { + field bits<32> Inst; + field bits<32> SoftFail = 0; + + bits<16> BD2; + + let Inst{31-16} = op; + let Inst{15-0} = BD2; +} + //===----------------------------------------------------------------------===// // Instruction definitions with semantics //===----------------------------------------------------------------------===// Index: llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZInstrInfo.td +++ llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1362,6 +1362,60 @@ let Defs = [CC] in { } //===----------------------------------------------------------------------===// +// Transactional execution +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureTransactionalExecution] in { + // Transaction Begin + let hasSideEffects = 1, mayStore = 1, + usesCustomInserter = 1, Defs = [CC] in { + def TBEGIN : InstSIL<0xE560, + (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), + "tbegin\t$BD1, $I2", + [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>; + def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), + [(z_tbegin_nofloat bdaddr12only:$BD1, + imm32zx16:$I2)]>; + def TBEGINC : InstSIL<0xE561, + (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), + "tbeginc\t$BD1, $I2", + [(int_s390_tbeginc bdaddr12only:$BD1, + imm32zx16:$I2)]>; + } + + // Transaction End + let hasSideEffects = 1, Defs = [CC], BD2 = 0 in + def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>; + + // Transaction Abort + let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in + def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2), + "tabort\t$BD2", + [(int_s390_tabort bdaddr12only:$BD2)]>; + + // Nontransactional Store + let hasSideEffects = 1 in + def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; + + // Extract Transaction Nesting Depth + let hasSideEffects = 1 in + def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>; +} + +//===----------------------------------------------------------------------===// +// Processor assist +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureProcessorAssist] in { + let hasSideEffects = 1, R4 = 0 in + def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3), + "ppa\t$R1, $R2, $R3", []>; + def : Pat<(int_s390_ppa_txassist GR32:$src), + (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), + 0, 1)>; +} + +//===----------------------------------------------------------------------===// // Miscellaneous Instructions. //===----------------------------------------------------------------------===// Index: llvm-head/lib/Target/SystemZ/SystemZProcessors.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZProcessors.td +++ llvm-head/lib/Target/SystemZ/SystemZProcessors.td @@ -60,6 +60,16 @@ def FeatureMiscellaneousExtensions : Sys "Assume that the miscellaneous-extensions facility is installed" >; +def FeatureTransactionalExecution : SystemZFeature< + "transactional-execution", "TransactionalExecution", + "Assume that the transactional-execution facility is installed" +>; + +def FeatureProcessorAssist : SystemZFeature< + "processor-assist", "ProcessorAssist", + "Assume that the processor-assist facility is installed" +>; + def : Processor<"generic", NoItineraries, []>; def : Processor<"z10", NoItineraries, []>; def : Processor<"z196", NoItineraries, @@ -70,4 +80,5 @@ def : Processor<"zEC12", NoItineraries, [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord, FeatureFPExtension, FeaturePopulationCount, FeatureFastSerialization, FeatureInterlockedAccess1, - FeatureMiscellaneousExtensions]>; + FeatureMiscellaneousExtensions, + FeatureTransactionalExecution, FeatureProcessorAssist]>; Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.cpp +++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -40,6 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false), HasPopulationCount(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), + HasTransactionalExecution(false), HasProcessorAssist(false), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {} Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.h =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.h +++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.h @@ -42,6 +42,8 @@ protected: bool HasFastSerialization; bool HasInterlockedAccess1; bool HasMiscellaneousExtensions; + bool HasTransactionalExecution; + bool HasProcessorAssist; private: Triple TargetTriple; @@ -102,6 +104,12 @@ public: return HasMiscellaneousExtensions; } + // Return true if the target has the transactional-execution facility. + bool hasTransactionalExecution() const { return HasTransactionalExecution; } + + // Return true if the target has the processor-assist facility. + bool hasProcessorAssist() const { return HasProcessorAssist; } + // Return true if GV can be accessed using LARL for reloc model RM // and code model CM. bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM, Index: llvm-head/lib/Support/Triple.cpp =================================================================== --- llvm-head.orig/lib/Support/Triple.cpp +++ llvm-head/lib/Support/Triple.cpp @@ -92,7 +92,7 @@ const char *Triple::getArchTypePrefix(Ar case sparcv9: case sparc: return "sparc"; - case systemz: return "systemz"; + case systemz: return "s390"; case x86: case x86_64: return "x86"; Index: llvm-head/include/llvm/IR/Intrinsics.td =================================================================== --- llvm-head.orig/include/llvm/IR/Intrinsics.td +++ llvm-head/include/llvm/IR/Intrinsics.td @@ -634,3 +634,4 @@ include "llvm/IR/IntrinsicsNVVM.td" include "llvm/IR/IntrinsicsMips.td" include "llvm/IR/IntrinsicsR600.td" include "llvm/IR/IntrinsicsBPF.td" +include "llvm/IR/IntrinsicsSystemZ.td" Index: llvm-head/include/llvm/IR/IntrinsicsSystemZ.td =================================================================== --- /dev/null +++ llvm-head/include/llvm/IR/IntrinsicsSystemZ.td @@ -0,0 +1,46 @@ +//===- IntrinsicsSystemZ.td - Defines SystemZ intrinsics ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines all of the SystemZ-specific intrinsics. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// +// Transactional-execution intrinsics +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "s390" in { + def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], + [IntrNoDuplicate]>; + + def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty], + [llvm_ptr_ty, llvm_i32_ty], + [IntrNoDuplicate]>; + + def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], + [IntrNoDuplicate]>; + + def int_s390_tabort : Intrinsic<[], [llvm_i64_ty], + [IntrNoReturn, Throws]>; + + def int_s390_tend : GCCBuiltin<"__builtin_tend">, + Intrinsic<[llvm_i32_ty], []>; + + def int_s390_etnd : GCCBuiltin<"__builtin_tx_nesting_depth">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + + def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty], + [IntrReadWriteArgMem]>; + + def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">, + Intrinsic<[], [llvm_i32_ty]>; +} + Index: llvm-head/lib/Target/SystemZ/SystemZ.h =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZ.h +++ llvm-head/lib/Target/SystemZ/SystemZ.h @@ -68,6 +68,18 @@ const unsigned CCMASK_TM_MSB_0 = C const unsigned CCMASK_TM_MSB_1 = CCMASK_2 | CCMASK_3; const unsigned CCMASK_TM = CCMASK_ANY; +// Condition-code mask assignments for TRANSACTION_BEGIN. +const unsigned CCMASK_TBEGIN_STARTED = CCMASK_0; +const unsigned CCMASK_TBEGIN_INDETERMINATE = CCMASK_1; +const unsigned CCMASK_TBEGIN_TRANSIENT = CCMASK_2; +const unsigned CCMASK_TBEGIN_PERSISTENT = CCMASK_3; +const unsigned CCMASK_TBEGIN = CCMASK_ANY; + +// Condition-code mask assignments for TRANSACTION_END. +const unsigned CCMASK_TEND_TX = CCMASK_0; +const unsigned CCMASK_TEND_NOTX = CCMASK_2; +const unsigned CCMASK_TEND = CCMASK_TEND_TX | CCMASK_TEND_NOTX; + // The position of the low CC bit in an IPM result. const unsigned IPM_CC = 28; Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.h =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.h +++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.h @@ -146,6 +146,15 @@ enum { // Perform a serialization operation. (BCR 15,0 or BCR 14,0.) SERIALIZE, + // Transaction begin. The first operand is the chain, the second + // the TDB pointer, and the third the immediate control field. + // Returns chain and glue. + TBEGIN, + TBEGIN_NOFLOAT, + + // Transaction end. Just the chain operand. Returns chain and glue. + TEND, + // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or // ATOMIC_LOAD_<op>. // @@ -318,6 +327,7 @@ private: SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; // If the last instruction before MBBI in MBB was some form of COMPARE, // try to replace it with a COMPARE AND BRANCH just before MBBI. @@ -355,6 +365,10 @@ private: MachineBasicBlock *emitStringWrapper(MachineInstr *MI, MachineBasicBlock *BB, unsigned Opcode) const; + MachineBasicBlock *emitTransactionBegin(MachineInstr *MI, + MachineBasicBlock *MBB, + unsigned Opcode, + bool NoFloat) const; }; } // end namespace llvm Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.cpp +++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/IR/Intrinsics.h" #include <cctype> using namespace llvm; @@ -304,6 +305,9 @@ SystemZTargetLowering::SystemZTargetLowe // Codes for which we want to perform some z-specific combinations. setTargetDAGCombine(ISD::SIGN_EXTEND); + // Handle intrinsics. + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); + // We want to use MVC in preference to even a single load/store pair. MaxStoresPerMemcpy = 0; MaxStoresPerMemcpyOptSize = 0; @@ -1031,6 +1035,53 @@ prepareVolatileOrAtomicLoad(SDValue Chai return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain); } +// Return true if Op is an intrinsic node with chain that returns the CC value +// as its only (other) argument. Provide the associated SystemZISD opcode and +// the mask of valid CC values if so. +static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode, + unsigned &CCValid) { + unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); + switch (Id) { + case Intrinsic::s390_tbegin: + Opcode = SystemZISD::TBEGIN; + CCValid = SystemZ::CCMASK_TBEGIN; + return true; + + case Intrinsic::s390_tbegin_nofloat: + Opcode = SystemZISD::TBEGIN_NOFLOAT; + CCValid = SystemZ::CCMASK_TBEGIN; + return true; + + case Intrinsic::s390_tend: + Opcode = SystemZISD::TEND; + CCValid = SystemZ::CCMASK_TEND; + return true; + + default: + return false; + } +} + +// Emit an intrinsic with chain with a glued value instead of its CC result. +static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op, + unsigned Opcode) { + // Copy all operands except the intrinsic ID. + unsigned NumOps = Op.getNumOperands(); + SmallVector<SDValue, 6> Ops; + Ops.reserve(NumOps - 1); + Ops.push_back(Op.getOperand(0)); + for (unsigned I = 2; I < NumOps; ++I) + Ops.push_back(Op.getOperand(I)); + + assert(Op->getNumValues() == 2 && "Expected only CC result and chain"); + SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue); + SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops); + SDValue OldChain = SDValue(Op.getNode(), 1); + SDValue NewChain = SDValue(Intr.getNode(), 0); + DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain); + return Intr; +} + // CC is a comparison that will be implemented using an integer or // floating-point comparison. Return the condition code mask for // a branch on true. In the integer case, CCMASK_CMP_UO is set for @@ -1588,9 +1639,53 @@ static void adjustForTestUnderMask(Selec C.CCMask = NewCCMask; } +// Return a Comparison that tests the condition-code result of intrinsic +// node Call against constant integer CC using comparison code Cond. +// Opcode is the opcode of the SystemZISD operation for the intrinsic +// and CCValid is the set of possible condition-code results. +static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode, + SDValue Call, unsigned CCValid, uint64_t CC, + ISD::CondCode Cond) { + Comparison C(Call, SDValue()); + C.Opcode = Opcode; + C.CCValid = CCValid; + if (Cond == ISD::SETEQ) + // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3. + C.CCMask = CC < 4 ? 1 << (3 - CC) : 0; + else if (Cond == ISD::SETNE) + // ...and the inverse of that. + C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1; + else if (Cond == ISD::SETLT || Cond == ISD::SETULT) + // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3, + // always true for CC>3. + C.CCMask = CC < 4 ? -1 << (4 - CC) : -1; + else if (Cond == ISD::SETGE || Cond == ISD::SETUGE) + // ...and the inverse of that. + C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0; + else if (Cond == ISD::SETLE || Cond == ISD::SETULE) + // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true), + // always true for CC>3. + C.CCMask = CC < 4 ? -1 << (3 - CC) : -1; + else if (Cond == ISD::SETGT || Cond == ISD::SETUGT) + // ...and the inverse of that. + C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0; + else + llvm_unreachable("Unexpected integer comparison type"); + C.CCMask &= CCValid; + return C; +} + // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1. static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1, ISD::CondCode Cond) { + if (CmpOp1.getOpcode() == ISD::Constant) { + uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue(); + unsigned Opcode, CCValid; + if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN && + CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) && + isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid)) + return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond); + } Comparison C(CmpOp0, CmpOp1); C.CCMask = CCMaskForCondCode(Cond); if (C.Op0.getValueType().isFloatingPoint()) { @@ -1632,6 +1727,17 @@ static Comparison getCmp(SelectionDAG &D // Emit the comparison instruction described by C. static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) { + if (!C.Op1.getNode()) { + SDValue Op; + switch (C.Op0.getOpcode()) { + case ISD::INTRINSIC_W_CHAIN: + Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode); + break; + default: + llvm_unreachable("Invalid comparison operands"); + } + return SDValue(Op.getNode(), Op->getNumValues() - 1); + } if (C.Opcode == SystemZISD::ICMP) return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1, DAG.getConstant(C.ICmpType, MVT::i32)); @@ -1713,7 +1819,6 @@ SDValue SystemZTargetLowering::lowerSETC } SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const { - SDValue Chain = Op.getOperand(0); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); SDValue CmpOp0 = Op.getOperand(2); SDValue CmpOp1 = Op.getOperand(3); @@ -1723,7 +1828,7 @@ SDValue SystemZTargetLowering::lowerBR_C Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC)); SDValue Glue = emitCmp(DAG, DL, C); return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(), - Chain, DAG.getConstant(C.CCValid, MVT::i32), + Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32), DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue); } @@ -2561,6 +2666,30 @@ SDValue SystemZTargetLowering::lowerPREF Node->getMemoryVT(), Node->getMemOperand()); } +// Return an i32 that contains the value of CC immediately after After, +// whose final operand must be MVT::Glue. +static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) { + SDValue Glue = SDValue(After, After->getNumValues() - 1); + SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue); + return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM, + DAG.getConstant(SystemZ::IPM_CC, MVT::i32)); +} + +SDValue +SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, + SelectionDAG &DAG) const { + unsigned Opcode, CCValid; + if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) { + assert(Op->getNumValues() == 2 && "Expected only CC result and chain"); + SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode); + SDValue CC = getCCResult(DAG, Glued.getNode()); + DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC); + return SDValue(); + } + + return SDValue(); +} + SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -2634,6 +2763,8 @@ SDValue SystemZTargetLowering::LowerOper return lowerSTACKRESTORE(Op, DAG); case ISD::PREFETCH: return lowerPREFETCH(Op, DAG); + case ISD::INTRINSIC_W_CHAIN: + return lowerINTRINSIC_W_CHAIN(Op, DAG); default: llvm_unreachable("Unexpected node to lower"); } @@ -2674,6 +2805,9 @@ const char *SystemZTargetLowering::getTa OPCODE(SEARCH_STRING); OPCODE(IPM); OPCODE(SERIALIZE); + OPCODE(TBEGIN); + OPCODE(TBEGIN_NOFLOAT); + OPCODE(TEND); OPCODE(ATOMIC_SWAPW); OPCODE(ATOMIC_LOADW_ADD); OPCODE(ATOMIC_LOADW_SUB); @@ -3501,6 +3635,50 @@ SystemZTargetLowering::emitStringWrapper return DoneMBB; } +// Update TBEGIN instruction with final opcode and register clobbers. +MachineBasicBlock * +SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI, + MachineBasicBlock *MBB, + unsigned Opcode, + bool NoFloat) const { + MachineFunction &MF = *MBB->getParent(); + const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); + const SystemZInstrInfo *TII = Subtarget.getInstrInfo(); + + // Update opcode. + MI->setDesc(TII->get(Opcode)); + + // We cannot handle a TBEGIN that clobbers the stack or frame pointer. + // Make sure to add the corresponding GRSM bits if they are missing. + uint64_t Control = MI->getOperand(2).getImm(); + static const unsigned GPRControlBit[16] = { + 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000, + 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100 + }; + Control |= GPRControlBit[15]; + if (TFI->hasFP(MF)) + Control |= GPRControlBit[11]; + MI->getOperand(2).setImm(Control); + + // Add GPR clobbers. + for (int I = 0; I < 16; I++) { + if ((Control & GPRControlBit[I]) == 0) { + unsigned Reg = SystemZMC::GR64Regs[I]; + MI->addOperand(MachineOperand::CreateReg(Reg, true, true)); + } + } + + // Add FPR clobbers. + if (!NoFloat && (Control & 4) != 0) { + for (int I = 0; I < 16; I++) { + unsigned Reg = SystemZMC::FP64Regs[I]; + MI->addOperand(MachineOperand::CreateReg(Reg, true, true)); + } + } + + return MBB; +} + MachineBasicBlock *SystemZTargetLowering:: EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const { switch (MI->getOpcode()) { @@ -3742,6 +3920,12 @@ EmitInstrWithCustomInserter(MachineInstr return emitStringWrapper(MI, MBB, SystemZ::MVST); case SystemZ::SRSTLoop: return emitStringWrapper(MI, MBB, SystemZ::SRST); + case SystemZ::TBEGIN: + return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false); + case SystemZ::TBEGIN_nofloat: + return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true); + case SystemZ::TBEGINC: + return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true); default: llvm_unreachable("Unexpected instr type to insert"); } Index: llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll =================================================================== --- /dev/null +++ llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll @@ -0,0 +1,352 @@ +; Test transactional-execution intrinsics. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s + +declare i32 @llvm.s390.tbegin(i8 *, i32) +declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32) +declare void @llvm.s390.tbeginc(i8 *, i32) +declare i32 @llvm.s390.tend() +declare void @llvm.s390.tabort(i64) +declare void @llvm.s390.ntstg(i64, i64 *) +declare i32 @llvm.s390.etnd() +declare void @llvm.s390.ppa.txassist(i32) + +; TBEGIN. +define void @test_tbegin() { +; CHECK-LABEL: test_tbegin: +; CHECK-NOT: stmg +; CHECK: std %f8, +; CHECK: std %f9, +; CHECK: std %f10, +; CHECK: std %f11, +; CHECK: std %f12, +; CHECK: std %f13, +; CHECK: std %f14, +; CHECK: std %f15, +; CHECK: tbegin 0, 65292 +; CHECK: ld %f8, +; CHECK: ld %f9, +; CHECK: ld %f10, +; CHECK: ld %f11, +; CHECK: ld %f12, +; CHECK: ld %f13, +; CHECK: ld %f14, +; CHECK: ld %f15, +; CHECK: br %r14 + call i32 @llvm.s390.tbegin(i8 *null, i32 65292) + ret void +} + +; TBEGIN (nofloat). +define void @test_tbegin_nofloat1() { +; CHECK-LABEL: test_tbegin_nofloat1: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + ret void +} + +; TBEGIN (nofloat) with integer CC return value. +define i32 @test_tbegin_nofloat2() { +; CHECK-LABEL: test_tbegin_nofloat2: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + ret i32 %res +} + +; TBEGIN (nofloat) with implicit CC check. +define void @test_tbegin_nofloat3(i32 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat3: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: jnh {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; TBEGIN (nofloat) with dual CC use. +define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat4: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: mvhi 0(%r3), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %res +} + +; TBEGIN (nofloat) with register. +define void @test_tbegin_nofloat5(i8 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat5: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0(%r2), 65292 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292) + ret void +} + +; TBEGIN (nofloat) with GRSM 0x0f00. +define void @test_tbegin_nofloat6() { +; CHECK-LABEL: test_tbegin_nofloat6: +; CHECK: stmg %r6, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 3840 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xf100. +define void @test_tbegin_nofloat7() { +; CHECK-LABEL: test_tbegin_nofloat7: +; CHECK: stmg %r8, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 61696 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically. +define void @test_tbegin_nofloat8() { +; CHECK-LABEL: test_tbegin_nofloat8: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65280 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed. +define void @test_tbegin_nofloat9() { +; CHECK-LABEL: test_tbegin_nofloat9: +; CHECK: stmg %r10, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 64256 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically. +define void @test_tbegin_nofloat10(i64 %n) { +; CHECK-LABEL: test_tbegin_nofloat10: +; CHECK: stmg %r11, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 65280 +; CHECK: br %r14 + %buf = alloca i8, i64 %n + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256) + ret void +} + +; TBEGINC. +define void @test_tbeginc() { +; CHECK-LABEL: test_tbeginc: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbeginc 0, 65288 +; CHECK: br %r14 + call void @llvm.s390.tbeginc(i8 *null, i32 65288) + ret void +} + +; TEND with integer CC return value. +define i32 @test_tend1() { +; CHECK-LABEL: test_tend1: +; CHECK: tend +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + ret i32 %res +} + +; TEND with implicit CC check. +define void @test_tend3(i32 *%ptr) { +; CHECK-LABEL: test_tend3: +; CHECK: tend +; CHECK: je {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; TEND with dual CC use. +define i32 @test_tend2(i32 %pad, i32 *%ptr) { +; CHECK-LABEL: test_tend2: +; CHECK: tend +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: mvhi 0(%r3), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %res +} + +; TABORT with register only. +define void @test_tabort1(i64 %val) { +; CHECK-LABEL: test_tabort1: +; CHECK: tabort 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 %val) + ret void +} + +; TABORT with immediate only. +define void @test_tabort2(i64 %val) { +; CHECK-LABEL: test_tabort2: +; CHECK: tabort 1234 +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 1234) + ret void +} + +; TABORT with register + immediate. +define void @test_tabort3(i64 %val) { +; CHECK-LABEL: test_tabort3: +; CHECK: tabort 1234(%r2) +; CHECK: br %r14 + %sum = add i64 %val, 1234 + call void @llvm.s390.tabort(i64 %sum) + ret void +} + +; TABORT with out-of-range immediate. +define void @test_tabort4(i64 %val) { +; CHECK-LABEL: test_tabort4: +; CHECK: tabort 0({{%r[1-5]}}) +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 4096) + ret void +} + +; NTSTG with base pointer only. +define void @test_ntstg1(i64 *%ptr, i64 %val) { +; CHECK-LABEL: test_ntstg1: +; CHECK: ntstg %r3, 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with base and index. +; Check that VSTL doesn't allow an index. +define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) { +; CHECK-LABEL: test_ntstg2: +; CHECK: sllg [[REG:%r[1-5]]], %r3, 3 +; CHECK: ntstg %r4, 0([[REG]],%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 %index + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with the highest in-range displacement. +define void @test_ntstg3(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg3: +; CHECK: ntstg %r3, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 65535 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with an out-of-range positive displacement. +define void @test_ntstg4(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg4: +; CHECK: ntstg %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 65536 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with the lowest in-range displacement. +define void @test_ntstg5(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg5: +; CHECK: ntstg %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 -65536 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with an out-of-range negative displacement. +define void @test_ntstg6(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg6: +; CHECK: ntstg %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 -65537 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; ETND. +define i32 @test_etnd() { +; CHECK-LABEL: test_etnd: +; CHECK: etnd %r2 +; CHECK: br %r14 + %res = call i32 @llvm.s390.etnd() + ret i32 %res +} + +; PPA (Transaction-Abort Assist) +define void @test_ppa_txassist(i32 %val) { +; CHECK-LABEL: test_ppa_txassist: +; CHECK: ppa %r2, 0, 1 +; CHECK: br %r14 + call void @llvm.s390.ppa.txassist(i32 %val) + ret void +} + Index: llvm-head/test/MC/SystemZ/insn-bad-zEC12.s =================================================================== --- llvm-head.orig/test/MC/SystemZ/insn-bad-zEC12.s +++ llvm-head/test/MC/SystemZ/insn-bad-zEC12.s @@ -3,6 +3,22 @@ # RUN: FileCheck < %t %s #CHECK: error: invalid operand +#CHECK: ntstg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ntstg %r0, 524288 + + ntstg %r0, -524289 + ntstg %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: ppa %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: ppa %r0, %r0, 16 + + ppa %r0, %r0, -1 + ppa %r0, %r0, 16 + +#CHECK: error: invalid operand #CHECK: risbgn %r0,%r0,0,0,-1 #CHECK: error: invalid operand #CHECK: risbgn %r0,%r0,0,0,64 @@ -22,3 +38,47 @@ risbgn %r0,%r0,-1,0,0 risbgn %r0,%r0,256,0,0 +#CHECK: error: invalid operand +#CHECK: tabort -1 +#CHECK: error: invalid operand +#CHECK: tabort 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: tabort 0(%r1,%r2) + + tabort -1 + tabort 4096 + tabort 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: tbegin -1, 0 +#CHECK: error: invalid operand +#CHECK: tbegin 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: tbegin 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: tbegin 0, -1 +#CHECK: error: invalid operand +#CHECK: tbegin 0, 65536 + + tbegin -1, 0 + tbegin 4096, 0 + tbegin 0(%r1,%r2), 0 + tbegin 0, -1 + tbegin 0, 65536 + +#CHECK: error: invalid operand +#CHECK: tbeginc -1, 0 +#CHECK: error: invalid operand +#CHECK: tbeginc 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: tbeginc 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: tbeginc 0, -1 +#CHECK: error: invalid operand +#CHECK: tbeginc 0, 65536 + + tbeginc -1, 0 + tbeginc 4096, 0 + tbeginc 0(%r1,%r2), 0 + tbeginc 0, -1 + tbeginc 0, 65536 Index: llvm-head/test/MC/SystemZ/insn-good-zEC12.s =================================================================== --- llvm-head.orig/test/MC/SystemZ/insn-good-zEC12.s +++ llvm-head/test/MC/SystemZ/insn-good-zEC12.s @@ -1,6 +1,48 @@ # For zEC12 and above. # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s +#CHECK: etnd %r0 # encoding: [0xb2,0xec,0x00,0x00] +#CHECK: etnd %r15 # encoding: [0xb2,0xec,0x00,0xf0] +#CHECK: etnd %r7 # encoding: [0xb2,0xec,0x00,0x70] + + etnd %r0 + etnd %r15 + etnd %r7 + +#CHECK: ntstg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25] +#CHECK: ntstg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25] +#CHECK: ntstg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25] +#CHECK: ntstg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25] +#CHECK: ntstg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25] +#CHECK: ntstg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25] +#CHECK: ntstg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25] +#CHECK: ntstg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25] +#CHECK: ntstg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25] +#CHECK: ntstg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25] + + ntstg %r0, -524288 + ntstg %r0, -1 + ntstg %r0, 0 + ntstg %r0, 1 + ntstg %r0, 524287 + ntstg %r0, 0(%r1) + ntstg %r0, 0(%r15) + ntstg %r0, 524287(%r1,%r15) + ntstg %r0, 524287(%r15,%r1) + ntstg %r15, 0 + +#CHECK: ppa %r0, %r0, 0 # encoding: [0xb2,0xe8,0x00,0x00] +#CHECK: ppa %r0, %r0, 15 # encoding: [0xb2,0xe8,0xf0,0x00] +#CHECK: ppa %r0, %r15, 0 # encoding: [0xb2,0xe8,0x00,0x0f] +#CHECK: ppa %r4, %r6, 7 # encoding: [0xb2,0xe8,0x70,0x46] +#CHECK: ppa %r15, %r0, 0 # encoding: [0xb2,0xe8,0x00,0xf0] + + ppa %r0, %r0, 0 + ppa %r0, %r0, 15 + ppa %r0, %r15, 0 + ppa %r4, %r6, 7 + ppa %r15, %r0, 0 + #CHECK: risbgn %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x59] #CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59] #CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] @@ -17,3 +59,68 @@ risbgn %r15,%r0,0,0,0 risbgn %r4,%r5,6,7,8 +#CHECK: tabort 0 # encoding: [0xb2,0xfc,0x00,0x00] +#CHECK: tabort 0(%r1) # encoding: [0xb2,0xfc,0x10,0x00] +#CHECK: tabort 0(%r15) # encoding: [0xb2,0xfc,0xf0,0x00] +#CHECK: tabort 4095 # encoding: [0xb2,0xfc,0x0f,0xff] +#CHECK: tabort 4095(%r1) # encoding: [0xb2,0xfc,0x1f,0xff] +#CHECK: tabort 4095(%r15) # encoding: [0xb2,0xfc,0xff,0xff] + + tabort 0 + tabort 0(%r1) + tabort 0(%r15) + tabort 4095 + tabort 4095(%r1) + tabort 4095(%r15) + +#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00] +#CHECK: tbegin 4095, 0 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00] +#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00] +#CHECK: tbegin 0, 1 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01] +#CHECK: tbegin 0, 32767 # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff] +#CHECK: tbegin 0, 32768 # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00] +#CHECK: tbegin 0, 65535 # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff] +#CHECK: tbegin 0(%r1), 42 # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a] +#CHECK: tbegin 0(%r15), 42 # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a] +#CHECK: tbegin 4095(%r1), 42 # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a] +#CHECK: tbegin 4095(%r15), 42 # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a] + + tbegin 0, 0 + tbegin 4095, 0 + tbegin 0, 0 + tbegin 0, 1 + tbegin 0, 32767 + tbegin 0, 32768 + tbegin 0, 65535 + tbegin 0(%r1), 42 + tbegin 0(%r15), 42 + tbegin 4095(%r1), 42 + tbegin 4095(%r15), 42 + +#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00] +#CHECK: tbeginc 4095, 0 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00] +#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00] +#CHECK: tbeginc 0, 1 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01] +#CHECK: tbeginc 0, 32767 # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff] +#CHECK: tbeginc 0, 32768 # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00] +#CHECK: tbeginc 0, 65535 # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff] +#CHECK: tbeginc 0(%r1), 42 # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a] +#CHECK: tbeginc 0(%r15), 42 # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a] +#CHECK: tbeginc 4095(%r1), 42 # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a] +#CHECK: tbeginc 4095(%r15), 42 # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a] + + tbeginc 0, 0 + tbeginc 4095, 0 + tbeginc 0, 0 + tbeginc 0, 1 + tbeginc 0, 32767 + tbeginc 0, 32768 + tbeginc 0, 65535 + tbeginc 0(%r1), 42 + tbeginc 0(%r15), 42 + tbeginc 4095(%r1), 42 + tbeginc 4095(%r15), 42 + +#CHECK: tend # encoding: [0xb2,0xf8,0x00,0x00] + + tend Index: llvm-head/test/MC/SystemZ/insn-bad-z196.s =================================================================== --- llvm-head.orig/test/MC/SystemZ/insn-bad-z196.s +++ llvm-head/test/MC/SystemZ/insn-bad-z196.s @@ -244,6 +244,11 @@ cxlgbr %f0, 16, %r0, 0 cxlgbr %f2, 0, %r0, 0 +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: etnd %r7 + + etnd %r7 + #CHECK: error: invalid operand #CHECK: fidbra %f0, 0, %f0, -1 #CHECK: error: invalid operand @@ -546,6 +551,16 @@ locr %r0,%r0,-1 locr %r0,%r0,16 +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: ntstg %r0, 524287(%r1,%r15) + + ntstg %r0, 524287(%r1,%r15) + +#CHECK: error: {{(instruction requires: processor-assist)?}} +#CHECK: ppa %r4, %r6, 7 + + ppa %r4, %r6, 7 + #CHECK: error: {{(instruction requires: miscellaneous-extensions)?}} #CHECK: risbgn %r1, %r2, 0, 0, 0 @@ -690,3 +705,24 @@ stocg %r0,-524289,1 stocg %r0,524288,1 stocg %r0,0(%r1,%r2),1 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tabort 4095(%r1) + + tabort 4095(%r1) + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tbegin 4095(%r1), 42 + + tbegin 4095(%r1), 42 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tbeginc 4095(%r1), 42 + + tbeginc 4095(%r1), 42 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tend + + tend + Index: llvm-head/test/MC/Disassembler/SystemZ/insns.txt =================================================================== --- llvm-head.orig/test/MC/Disassembler/SystemZ/insns.txt +++ llvm-head/test/MC/Disassembler/SystemZ/insns.txt @@ -2503,6 +2503,15 @@ # CHECK: ear %r15, %a15 0xb2 0x4f 0x00 0xff +# CHECK: etnd %r0 +0xb2 0xec 0x00 0x00 + +# CHECK: etnd %r15 +0xb2 0xec 0x00 0xf0 + +# CHECK: etnd %r7 +0xb2 0xec 0x00 0x70 + # CHECK: fidbr %f0, 0, %f0 0xb3 0x5f 0x00 0x00 @@ -6034,6 +6043,36 @@ # CHECK: ny %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x54 +# CHECK: ntstg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x25 + +# CHECK: ntstg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x25 + +# CHECK: ntstg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x25 + +# CHECK: ntstg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x25 + +# CHECK: ntstg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x25 + +# CHECK: ntstg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x25 + +# CHECK: ntstg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x25 + # CHECK: oc 0(1), 0 0xd6 0x00 0x00 0x00 0x00 0x00 @@ -6346,6 +6385,21 @@ # CHECK: popcnt %r7, %r8 0xb9 0xe1 0x00 0x78 +# CHECK: ppa %r0, %r0, 0 +0xb2 0xe8 0x00 0x00 + +# CHECK: ppa %r0, %r0, 15 +0xb2 0xe8 0xf0 0x00 + +# CHECK: ppa %r0, %r15, 0 +0xb2 0xe8 0x00 0x0f + +# CHECK: ppa %r4, %r6, 7 +0xb2 0xe8 0x70 0x46 + +# CHECK: ppa %r15, %r0, 0 +0xb2 0xe8 0x00 0xf0 + # CHECK: risbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x55 @@ -8062,6 +8116,93 @@ # CHECK: sy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x5b +# CHECK: tabort 0 +0xb2 0xfc 0x00 0x00 + +# CHECK: tabort 0(%r1) +0xb2 0xfc 0x10 0x00 + +# CHECK: tabort 0(%r15) +0xb2 0xfc 0xf0 0x00 + +# CHECK: tabort 4095 +0xb2 0xfc 0x0f 0xff + +# CHECK: tabort 4095(%r1) +0xb2 0xfc 0x1f 0xff + +# CHECK: tabort 4095(%r15) +0xb2 0xfc 0xff 0xff + +# CHECK: tbegin 0, 0 +0xe5 0x60 0x00 0x00 0x00 0x00 + +# CHECK: tbegin 4095, 0 +0xe5 0x60 0x0f 0xff 0x00 0x00 + +# CHECK: tbegin 0, 0 +0xe5 0x60 0x00 0x00 0x00 0x00 + +# CHECK: tbegin 0, 1 +0xe5 0x60 0x00 0x00 0x00 0x01 + +# CHECK: tbegin 0, 32767 +0xe5 0x60 0x00 0x00 0x7f 0xff + +# CHECK: tbegin 0, 32768 +0xe5 0x60 0x00 0x00 0x80 0x00 + +# CHECK: tbegin 0, 65535 +0xe5 0x60 0x00 0x00 0xff 0xff + +# CHECK: tbegin 0(%r1), 42 +0xe5 0x60 0x10 0x00 0x00 0x2a + +# CHECK: tbegin 0(%r15), 42 +0xe5 0x60 0xf0 0x00 0x00 0x2a + +# CHECK: tbegin 4095(%r1), 42 +0xe5 0x60 0x1f 0xff 0x00 0x2a + +# CHECK: tbegin 4095(%r15), 42 +0xe5 0x60 0xff 0xff 0x00 0x2a + +# CHECK: tbeginc 0, 0 +0xe5 0x61 0x00 0x00 0x00 0x00 + +# CHECK: tbeginc 4095, 0 +0xe5 0x61 0x0f 0xff 0x00 0x00 + +# CHECK: tbeginc 0, 0 +0xe5 0x61 0x00 0x00 0x00 0x00 + +# CHECK: tbeginc 0, 1 +0xe5 0x61 0x00 0x00 0x00 0x01 + +# CHECK: tbeginc 0, 32767 +0xe5 0x61 0x00 0x00 0x7f 0xff + +# CHECK: tbeginc 0, 32768 +0xe5 0x61 0x00 0x00 0x80 0x00 + +# CHECK: tbeginc 0, 65535 +0xe5 0x61 0x00 0x00 0xff 0xff + +# CHECK: tbeginc 0(%r1), 42 +0xe5 0x61 0x10 0x00 0x00 0x2a + +# CHECK: tbeginc 0(%r15), 42 +0xe5 0x61 0xf0 0x00 0x00 0x2a + +# CHECK: tbeginc 4095(%r1), 42 +0xe5 0x61 0x1f 0xff 0x00 0x2a + +# CHECK: tbeginc 4095(%r15), 42 +0xe5 0x61 0xff 0xff 0x00 0x2a + +# CHECK: tend +0xb2 0xf8 0x00 0x00 + # CHECK: tm 0, 0 0x91 0x00 0x00 0x00 llvm-svn: 233803
634 lines
29 KiB
TableGen
634 lines
29 KiB
TableGen
//===- Intrinsics.td - Defines all LLVM intrinsics ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines properties of all LLVM intrinsics.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/CodeGen/ValueTypes.td"
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//===----------------------------------------------------------------------===//
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// Properties we keep track of for intrinsics.
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//===----------------------------------------------------------------------===//
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class IntrinsicProperty;
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// Intr*Mem - Memory properties. An intrinsic is allowed to have at most one of
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// these properties set. They are listed from the most aggressive (best to use
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// if correct) to the least aggressive. If no property is set, the worst case
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// is assumed (it may read and write any memory it can get access to and it may
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// have other side effects).
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// IntrNoMem - The intrinsic does not access memory or have any other side
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// effects. It may be CSE'd deleted if dead, etc.
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def IntrNoMem : IntrinsicProperty;
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// IntrReadArgMem - This intrinsic reads only from memory that one of its
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// pointer-typed arguments points to, but may read an unspecified amount.
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def IntrReadArgMem : IntrinsicProperty;
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// IntrReadMem - This intrinsic reads from unspecified memory, so it cannot be
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// moved across stores. However, it can be reordered otherwise and can be
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// deleted if dead.
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def IntrReadMem : IntrinsicProperty;
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// IntrReadWriteArgMem - This intrinsic reads and writes only from memory that
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// one of its arguments points to, but may access an unspecified amount. The
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// reads and writes may be volatile, but except for this it has no other side
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// effects.
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def IntrReadWriteArgMem : IntrinsicProperty;
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// Commutative - This intrinsic is commutative: X op Y == Y op X.
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def Commutative : IntrinsicProperty;
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// Throws - This intrinsic can throw.
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def Throws : IntrinsicProperty;
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// NoCapture - The specified argument pointer is not captured by the intrinsic.
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class NoCapture<int argNo> : IntrinsicProperty {
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int ArgNo = argNo;
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}
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// ReadOnly - The specified argument pointer is not written to through the
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// pointer by the intrinsic.
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class ReadOnly<int argNo> : IntrinsicProperty {
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int ArgNo = argNo;
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}
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// ReadNone - The specified argument pointer is not dereferenced by the
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// intrinsic.
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class ReadNone<int argNo> : IntrinsicProperty {
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int ArgNo = argNo;
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}
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def IntrNoReturn : IntrinsicProperty;
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// IntrNoduplicate - Calls to this intrinsic cannot be duplicated.
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// Parallels the noduplicate attribute on LLVM IR functions.
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def IntrNoDuplicate : IntrinsicProperty;
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//===----------------------------------------------------------------------===//
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// Types used by intrinsics.
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//===----------------------------------------------------------------------===//
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class LLVMType<ValueType vt> {
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ValueType VT = vt;
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}
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class LLVMQualPointerType<LLVMType elty, int addrspace>
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: LLVMType<iPTR>{
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LLVMType ElTy = elty;
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int AddrSpace = addrspace;
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}
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class LLVMPointerType<LLVMType elty>
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: LLVMQualPointerType<elty, 0>;
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class LLVMAnyPointerType<LLVMType elty>
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: LLVMType<iPTRAny>{
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LLVMType ElTy = elty;
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}
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// Match the type of another intrinsic parameter. Number is an index into the
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// list of overloaded types for the intrinsic, excluding all the fixed types.
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// The Number value must refer to a previously listed type. For example:
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// Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyfloat_ty, LLVMMatchType<0>]>
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// has two overloaded types, the 2nd and 3rd arguments. LLVMMatchType<0>
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// refers to the first overloaded type, which is the 2nd argument.
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class LLVMMatchType<int num>
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: LLVMType<OtherVT>{
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int Number = num;
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}
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// Match the type of another intrinsic parameter that is expected to be based on
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// an integral type (i.e. either iN or <N x iM>), but change the scalar size to
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// be twice as wide or half as wide as the other type. This is only useful when
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// the intrinsic is overloaded, so the matched type should be declared as iAny.
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class LLVMExtendedType<int num> : LLVMMatchType<num>;
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class LLVMTruncatedType<int num> : LLVMMatchType<num>;
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class LLVMVectorSameWidth<int num, LLVMType elty>
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: LLVMMatchType<num> {
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ValueType ElTy = elty.VT;
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}
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class LLVMPointerTo<int num> : LLVMMatchType<num>;
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class LLVMVectorOfPointersToElt<int num> : LLVMMatchType<num>;
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// Match the type of another intrinsic parameter that is expected to be a
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// vector type, but change the element count to be half as many
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class LLVMHalfElementsVectorType<int num> : LLVMMatchType<num>;
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def llvm_void_ty : LLVMType<isVoid>;
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def llvm_any_ty : LLVMType<Any>;
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def llvm_anyint_ty : LLVMType<iAny>;
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def llvm_anyfloat_ty : LLVMType<fAny>;
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def llvm_anyvector_ty : LLVMType<vAny>;
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def llvm_i1_ty : LLVMType<i1>;
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def llvm_i8_ty : LLVMType<i8>;
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def llvm_i16_ty : LLVMType<i16>;
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def llvm_i32_ty : LLVMType<i32>;
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def llvm_i64_ty : LLVMType<i64>;
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def llvm_half_ty : LLVMType<f16>;
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def llvm_float_ty : LLVMType<f32>;
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def llvm_double_ty : LLVMType<f64>;
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def llvm_f80_ty : LLVMType<f80>;
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def llvm_f128_ty : LLVMType<f128>;
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def llvm_ppcf128_ty : LLVMType<ppcf128>;
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def llvm_ptr_ty : LLVMPointerType<llvm_i8_ty>; // i8*
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def llvm_ptrptr_ty : LLVMPointerType<llvm_ptr_ty>; // i8**
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def llvm_anyptr_ty : LLVMAnyPointerType<llvm_i8_ty>; // (space)i8*
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def llvm_empty_ty : LLVMType<OtherVT>; // { }
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def llvm_descriptor_ty : LLVMPointerType<llvm_empty_ty>; // { }*
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def llvm_metadata_ty : LLVMType<MetadataVT>; // !{...}
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def llvm_x86mmx_ty : LLVMType<x86mmx>;
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def llvm_ptrx86mmx_ty : LLVMPointerType<llvm_x86mmx_ty>; // <1 x i64>*
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def llvm_v2i1_ty : LLVMType<v2i1>; // 2 x i1
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def llvm_v4i1_ty : LLVMType<v4i1>; // 4 x i1
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def llvm_v8i1_ty : LLVMType<v8i1>; // 8 x i1
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def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1
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def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1
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def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1
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def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8
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def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8
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def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8
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def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8
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def llvm_v16i8_ty : LLVMType<v16i8>; // 16 x i8
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def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8
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def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8
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def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16
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def llvm_v2i16_ty : LLVMType<v2i16>; // 2 x i16
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def llvm_v4i16_ty : LLVMType<v4i16>; // 4 x i16
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def llvm_v8i16_ty : LLVMType<v8i16>; // 8 x i16
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def llvm_v16i16_ty : LLVMType<v16i16>; // 16 x i16
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def llvm_v32i16_ty : LLVMType<v32i16>; // 32 x i16
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def llvm_v1i32_ty : LLVMType<v1i32>; // 1 x i32
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def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32
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def llvm_v4i32_ty : LLVMType<v4i32>; // 4 x i32
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def llvm_v8i32_ty : LLVMType<v8i32>; // 8 x i32
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def llvm_v16i32_ty : LLVMType<v16i32>; // 16 x i32
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def llvm_v1i64_ty : LLVMType<v1i64>; // 1 x i64
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def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64
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def llvm_v4i64_ty : LLVMType<v4i64>; // 4 x i64
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def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64
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def llvm_v16i64_ty : LLVMType<v16i64>; // 16 x i64
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def llvm_v2f16_ty : LLVMType<v2f16>; // 2 x half (__fp16)
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def llvm_v4f16_ty : LLVMType<v4f16>; // 4 x half (__fp16)
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def llvm_v8f16_ty : LLVMType<v8f16>; // 8 x half (__fp16)
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def llvm_v1f32_ty : LLVMType<v1f32>; // 1 x float
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def llvm_v2f32_ty : LLVMType<v2f32>; // 2 x float
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def llvm_v4f32_ty : LLVMType<v4f32>; // 4 x float
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def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float
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def llvm_v16f32_ty : LLVMType<v16f32>; // 16 x float
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def llvm_v1f64_ty : LLVMType<v1f64>; // 1 x double
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def llvm_v2f64_ty : LLVMType<v2f64>; // 2 x double
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def llvm_v4f64_ty : LLVMType<v4f64>; // 4 x double
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def llvm_v8f64_ty : LLVMType<v8f64>; // 8 x double
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def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here
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//===----------------------------------------------------------------------===//
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// Intrinsic Definitions.
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//===----------------------------------------------------------------------===//
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// Intrinsic class - This is used to define one LLVM intrinsic. The name of the
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// intrinsic definition should start with "int_", then match the LLVM intrinsic
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// name with the "llvm." prefix removed, and all "."s turned into "_"s. For
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// example, llvm.bswap.i16 -> int_bswap_i16.
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//
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// * RetTypes is a list containing the return types expected for the
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// intrinsic.
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// * ParamTypes is a list containing the parameter types expected for the
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// intrinsic.
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// * Properties can be set to describe the behavior of the intrinsic.
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//
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class SDPatternOperator;
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class Intrinsic<list<LLVMType> ret_types,
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list<LLVMType> param_types = [],
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list<IntrinsicProperty> properties = [],
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string name = ""> : SDPatternOperator {
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string LLVMName = name;
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string TargetPrefix = ""; // Set to a prefix for target-specific intrinsics.
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list<LLVMType> RetTypes = ret_types;
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list<LLVMType> ParamTypes = param_types;
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list<IntrinsicProperty> Properties = properties;
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bit isTarget = 0;
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}
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/// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, this
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/// specifies the name of the builtin. This provides automatic CBE and CFE
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/// support.
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class GCCBuiltin<string name> {
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string GCCBuiltinName = name;
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}
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class MSBuiltin<string name> {
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string MSBuiltinName = name;
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}
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//===--------------- Variable Argument Handling Intrinsics ----------------===//
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//
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def int_vastart : Intrinsic<[], [llvm_ptr_ty], [], "llvm.va_start">;
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def int_vacopy : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], [],
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"llvm.va_copy">;
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def int_vaend : Intrinsic<[], [llvm_ptr_ty], [], "llvm.va_end">;
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//===------------------- Garbage Collection Intrinsics --------------------===//
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//
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def int_gcroot : Intrinsic<[],
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[llvm_ptrptr_ty, llvm_ptr_ty]>;
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def int_gcread : Intrinsic<[llvm_ptr_ty],
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[llvm_ptr_ty, llvm_ptrptr_ty],
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[IntrReadArgMem]>;
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def int_gcwrite : Intrinsic<[],
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[llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty],
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[IntrReadWriteArgMem, NoCapture<1>, NoCapture<2>]>;
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//===--------------------- Code Generator Intrinsics ----------------------===//
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//
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def int_returnaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_frameaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_frameescape : Intrinsic<[], [llvm_vararg_ty]>;
|
|
def int_framerecover : Intrinsic<[llvm_ptr_ty],
|
|
[llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
|
|
[IntrNoMem]>;
|
|
def int_read_register : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty],
|
|
[IntrNoMem], "llvm.read_register">;
|
|
def int_write_register : Intrinsic<[], [llvm_metadata_ty, llvm_anyint_ty],
|
|
[], "llvm.write_register">;
|
|
|
|
// Note: we treat stacksave/stackrestore as writemem because we don't otherwise
|
|
// model their dependencies on allocas.
|
|
def int_stacksave : Intrinsic<[llvm_ptr_ty]>,
|
|
GCCBuiltin<"__builtin_stack_save">;
|
|
def int_stackrestore : Intrinsic<[], [llvm_ptr_ty]>,
|
|
GCCBuiltin<"__builtin_stack_restore">;
|
|
|
|
// IntrReadWriteArgMem is more pessimistic than strictly necessary for prefetch,
|
|
// however it does conveniently prevent the prefetch from being reordered
|
|
// with respect to nearby accesses to the same memory.
|
|
def int_prefetch : Intrinsic<[],
|
|
[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty,
|
|
llvm_i32_ty],
|
|
[IntrReadWriteArgMem, NoCapture<0>]>;
|
|
def int_pcmarker : Intrinsic<[], [llvm_i32_ty]>;
|
|
|
|
def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>;
|
|
|
|
// The assume intrinsic is marked as arbitrarily writing so that proper
|
|
// control dependencies will be maintained.
|
|
def int_assume : Intrinsic<[], [llvm_i1_ty], []>;
|
|
|
|
// Stack Protector Intrinsic - The stackprotector intrinsic writes the stack
|
|
// guard to the correct place on the stack frame.
|
|
def int_stackprotector : Intrinsic<[], [llvm_ptr_ty, llvm_ptrptr_ty], []>;
|
|
def int_stackprotectorcheck : Intrinsic<[], [llvm_ptrptr_ty],
|
|
[IntrReadWriteArgMem]>;
|
|
|
|
// A counter increment for instrumentation based profiling.
|
|
def int_instrprof_increment : Intrinsic<[],
|
|
[llvm_ptr_ty, llvm_i64_ty,
|
|
llvm_i32_ty, llvm_i32_ty],
|
|
[]>;
|
|
|
|
//===------------------- Standard C Library Intrinsics --------------------===//
|
|
//
|
|
|
|
def int_memcpy : Intrinsic<[],
|
|
[llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
|
|
llvm_i32_ty, llvm_i1_ty],
|
|
[IntrReadWriteArgMem, NoCapture<0>, NoCapture<1>,
|
|
ReadOnly<1>]>;
|
|
def int_memmove : Intrinsic<[],
|
|
[llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
|
|
llvm_i32_ty, llvm_i1_ty],
|
|
[IntrReadWriteArgMem, NoCapture<0>, NoCapture<1>,
|
|
ReadOnly<1>]>;
|
|
def int_memset : Intrinsic<[],
|
|
[llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty,
|
|
llvm_i32_ty, llvm_i1_ty],
|
|
[IntrReadWriteArgMem, NoCapture<0>]>;
|
|
|
|
let Properties = [IntrNoMem] in {
|
|
def int_fma : Intrinsic<[llvm_anyfloat_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>,
|
|
LLVMMatchType<0>]>;
|
|
def int_fmuladd : Intrinsic<[llvm_anyfloat_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>,
|
|
LLVMMatchType<0>]>;
|
|
|
|
// These functions do not read memory, but are sensitive to the
|
|
// rounding mode. LLVM purposely does not model changes to the FP
|
|
// environment so they can be treated as readnone.
|
|
def int_sqrt : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_powi : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty]>;
|
|
def int_sin : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_cos : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_pow : Intrinsic<[llvm_anyfloat_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>]>;
|
|
def int_log : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_log10: Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_log2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_fabs : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_minnum : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>;
|
|
def int_maxnum : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>;
|
|
def int_copysign : Intrinsic<[llvm_anyfloat_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>]>;
|
|
def int_floor : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_ceil : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_trunc : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_rint : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_nearbyint : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
def int_round : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
|
|
}
|
|
|
|
// NOTE: these are internal interfaces.
|
|
def int_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
|
|
def int_longjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoReturn]>;
|
|
def int_sigsetjmp : Intrinsic<[llvm_i32_ty] , [llvm_ptr_ty, llvm_i32_ty]>;
|
|
def int_siglongjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoReturn]>;
|
|
|
|
// Internal interface for object size checking
|
|
def int_objectsize : Intrinsic<[llvm_anyint_ty], [llvm_anyptr_ty, llvm_i1_ty],
|
|
[IntrNoMem]>,
|
|
GCCBuiltin<"__builtin_object_size">;
|
|
|
|
//===------------------------- Expect Intrinsics --------------------------===//
|
|
//
|
|
def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
|
|
LLVMMatchType<0>], [IntrNoMem]>;
|
|
|
|
//===-------------------- Bit Manipulation Intrinsics ---------------------===//
|
|
//
|
|
|
|
// None of these intrinsics accesses memory at all.
|
|
let Properties = [IntrNoMem] in {
|
|
def int_bswap: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
|
|
def int_ctpop: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
|
|
def int_ctlz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty]>;
|
|
def int_cttz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty]>;
|
|
}
|
|
|
|
//===------------------------ Debugger Intrinsics -------------------------===//
|
|
//
|
|
|
|
// None of these intrinsics accesses memory at all...but that doesn't mean the
|
|
// optimizers can change them aggressively. Special handling needed in a few
|
|
// places.
|
|
let Properties = [IntrNoMem] in {
|
|
def int_dbg_declare : Intrinsic<[],
|
|
[llvm_metadata_ty,
|
|
llvm_metadata_ty,
|
|
llvm_metadata_ty]>;
|
|
def int_dbg_value : Intrinsic<[],
|
|
[llvm_metadata_ty, llvm_i64_ty,
|
|
llvm_metadata_ty,
|
|
llvm_metadata_ty]>;
|
|
}
|
|
|
|
//===------------------ Exception Handling Intrinsics----------------------===//
|
|
//
|
|
|
|
// The result of eh.typeid.for depends on the enclosing function, but inside a
|
|
// given function it is 'const' and may be CSE'd etc.
|
|
def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
|
|
|
|
def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;
|
|
def int_eh_return_i64 : Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>;
|
|
|
|
// eh.begincatch takes a pointer returned by a landingpad instruction and
|
|
// copies the exception object into the memory pointed to by the second
|
|
// parameter. If the second parameter is null, no copy occurs.
|
|
def int_eh_begincatch : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty],
|
|
[NoCapture<0>, NoCapture<1>]>;
|
|
def int_eh_endcatch : Intrinsic<[], []>;
|
|
|
|
// Represents the list of actions to take when an exception is thrown.
|
|
def int_eh_actions : Intrinsic<[llvm_ptr_ty], [llvm_vararg_ty], []>;
|
|
|
|
// Designates the provided static alloca as the unwind help object. Required
|
|
// for WinEH.
|
|
def int_eh_unwindhelp : Intrinsic<[], [llvm_ptr_ty], []>;
|
|
|
|
// __builtin_unwind_init is an undocumented GCC intrinsic that causes all
|
|
// callee-saved registers to be saved and restored (regardless of whether they
|
|
// are used) in the calling function. It is used by libgcc_eh.
|
|
def int_eh_unwind_init: Intrinsic<[]>,
|
|
GCCBuiltin<"__builtin_unwind_init">;
|
|
|
|
def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;
|
|
|
|
let Properties = [IntrNoMem] in {
|
|
def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>;
|
|
def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>;
|
|
}
|
|
def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>;
|
|
def int_eh_sjlj_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
|
|
def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty], [IntrNoReturn]>;
|
|
|
|
//===---------------- Generic Variable Attribute Intrinsics----------------===//
|
|
//
|
|
def int_var_annotation : Intrinsic<[],
|
|
[llvm_ptr_ty, llvm_ptr_ty,
|
|
llvm_ptr_ty, llvm_i32_ty],
|
|
[], "llvm.var.annotation">;
|
|
def int_ptr_annotation : Intrinsic<[LLVMAnyPointerType<llvm_anyint_ty>],
|
|
[LLVMMatchType<0>, llvm_ptr_ty, llvm_ptr_ty,
|
|
llvm_i32_ty],
|
|
[], "llvm.ptr.annotation">;
|
|
def int_annotation : Intrinsic<[llvm_anyint_ty],
|
|
[LLVMMatchType<0>, llvm_ptr_ty,
|
|
llvm_ptr_ty, llvm_i32_ty],
|
|
[], "llvm.annotation">;
|
|
|
|
//===------------------------ Trampoline Intrinsics -----------------------===//
|
|
//
|
|
def int_init_trampoline : Intrinsic<[],
|
|
[llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty],
|
|
[IntrReadWriteArgMem, NoCapture<0>]>,
|
|
GCCBuiltin<"__builtin_init_trampoline">;
|
|
|
|
def int_adjust_trampoline : Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty],
|
|
[IntrReadArgMem]>,
|
|
GCCBuiltin<"__builtin_adjust_trampoline">;
|
|
|
|
//===------------------------ Overflow Intrinsics -------------------------===//
|
|
//
|
|
|
|
// Expose the carry flag from add operations on two integrals.
|
|
def int_sadd_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>],
|
|
[IntrNoMem]>;
|
|
def int_uadd_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>],
|
|
[IntrNoMem]>;
|
|
|
|
def int_ssub_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>],
|
|
[IntrNoMem]>;
|
|
def int_usub_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>],
|
|
[IntrNoMem]>;
|
|
|
|
def int_smul_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>],
|
|
[IntrNoMem]>;
|
|
def int_umul_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
|
|
[LLVMMatchType<0>, LLVMMatchType<0>],
|
|
[IntrNoMem]>;
|
|
|
|
//===------------------------- Memory Use Markers -------------------------===//
|
|
//
|
|
def int_lifetime_start : Intrinsic<[],
|
|
[llvm_i64_ty, llvm_ptr_ty],
|
|
[IntrReadWriteArgMem, NoCapture<1>]>;
|
|
def int_lifetime_end : Intrinsic<[],
|
|
[llvm_i64_ty, llvm_ptr_ty],
|
|
[IntrReadWriteArgMem, NoCapture<1>]>;
|
|
def int_invariant_start : Intrinsic<[llvm_descriptor_ty],
|
|
[llvm_i64_ty, llvm_ptr_ty],
|
|
[IntrReadWriteArgMem, NoCapture<1>]>;
|
|
def int_invariant_end : Intrinsic<[],
|
|
[llvm_descriptor_ty, llvm_i64_ty,
|
|
llvm_ptr_ty],
|
|
[IntrReadWriteArgMem, NoCapture<2>]>;
|
|
|
|
//===------------------------ Stackmap Intrinsics -------------------------===//
|
|
//
|
|
def int_experimental_stackmap : Intrinsic<[],
|
|
[llvm_i64_ty, llvm_i32_ty, llvm_vararg_ty],
|
|
[Throws]>;
|
|
def int_experimental_patchpoint_void : Intrinsic<[],
|
|
[llvm_i64_ty, llvm_i32_ty,
|
|
llvm_ptr_ty, llvm_i32_ty,
|
|
llvm_vararg_ty],
|
|
[Throws]>;
|
|
def int_experimental_patchpoint_i64 : Intrinsic<[llvm_i64_ty],
|
|
[llvm_i64_ty, llvm_i32_ty,
|
|
llvm_ptr_ty, llvm_i32_ty,
|
|
llvm_vararg_ty],
|
|
[Throws]>;
|
|
|
|
|
|
//===------------------------ Garbage Collection Intrinsics ---------------===//
|
|
// These are documented in docs/Statepoint.rst
|
|
|
|
def int_experimental_gc_statepoint : Intrinsic<[llvm_i32_ty],
|
|
[llvm_anyptr_ty, llvm_i32_ty,
|
|
llvm_i32_ty, llvm_vararg_ty]>;
|
|
|
|
def int_experimental_gc_result : Intrinsic<[llvm_any_ty], [llvm_i32_ty]>;
|
|
def int_experimental_gc_relocate : Intrinsic<[llvm_anyptr_ty],
|
|
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
|
|
// Deprecated: will be removed in a couple of weeks
|
|
def int_experimental_gc_result_int : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty]>;
|
|
def int_experimental_gc_result_float : Intrinsic<[llvm_anyfloat_ty],
|
|
[llvm_i32_ty]>;
|
|
def int_experimental_gc_result_ptr : Intrinsic<[llvm_anyptr_ty], [llvm_i32_ty]>;
|
|
|
|
//===-------------------------- Other Intrinsics --------------------------===//
|
|
//
|
|
def int_flt_rounds : Intrinsic<[llvm_i32_ty]>,
|
|
GCCBuiltin<"__builtin_flt_rounds">;
|
|
def int_trap : Intrinsic<[], [], [IntrNoReturn]>,
|
|
GCCBuiltin<"__builtin_trap">;
|
|
def int_debugtrap : Intrinsic<[]>,
|
|
GCCBuiltin<"__builtin_debugtrap">;
|
|
|
|
// NOP: calls/invokes to this intrinsic are removed by codegen
|
|
def int_donothing : Intrinsic<[], [], [IntrNoMem]>;
|
|
|
|
// Intrisics to support half precision floating point format
|
|
let Properties = [IntrNoMem] in {
|
|
def int_convert_to_fp16 : Intrinsic<[llvm_i16_ty], [llvm_anyfloat_ty]>;
|
|
def int_convert_from_fp16 : Intrinsic<[llvm_anyfloat_ty], [llvm_i16_ty]>;
|
|
}
|
|
|
|
// These convert intrinsics are to support various conversions between
|
|
// various types with rounding and saturation. NOTE: avoid using these
|
|
// intrinsics as they might be removed sometime in the future and
|
|
// most targets don't support them.
|
|
def int_convertff : Intrinsic<[llvm_anyfloat_ty],
|
|
[llvm_anyfloat_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
def int_convertfsi : Intrinsic<[llvm_anyfloat_ty],
|
|
[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
def int_convertfui : Intrinsic<[llvm_anyfloat_ty],
|
|
[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
def int_convertsif : Intrinsic<[llvm_anyint_ty],
|
|
[llvm_anyfloat_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
def int_convertuif : Intrinsic<[llvm_anyint_ty],
|
|
[llvm_anyfloat_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
def int_convertss : Intrinsic<[llvm_anyint_ty],
|
|
[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
def int_convertsu : Intrinsic<[llvm_anyint_ty],
|
|
[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
def int_convertus : Intrinsic<[llvm_anyint_ty],
|
|
[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
def int_convertuu : Intrinsic<[llvm_anyint_ty],
|
|
[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;
|
|
|
|
// Clear cache intrinsic, default to ignore (ie. emit nothing)
|
|
// maps to void __clear_cache() on supporting platforms
|
|
def int_clear_cache : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty],
|
|
[], "llvm.clear_cache">;
|
|
|
|
//===-------------------------- Masked Intrinsics -------------------------===//
|
|
//
|
|
def int_masked_store : Intrinsic<[], [llvm_anyvector_ty, LLVMPointerTo<0>,
|
|
llvm_i32_ty,
|
|
LLVMVectorSameWidth<0, llvm_i1_ty>],
|
|
[IntrReadWriteArgMem]>;
|
|
|
|
def int_masked_load : Intrinsic<[llvm_anyvector_ty],
|
|
[LLVMPointerTo<0>, llvm_i32_ty,
|
|
LLVMVectorSameWidth<0, llvm_i1_ty>, LLVMMatchType<0>],
|
|
[IntrReadArgMem]>;
|
|
|
|
def int_masked_gather: Intrinsic<[llvm_anyvector_ty],
|
|
[LLVMVectorOfPointersToElt<0>, llvm_i32_ty,
|
|
LLVMVectorSameWidth<0, llvm_i1_ty>,
|
|
LLVMMatchType<0>],
|
|
[IntrReadArgMem]>;
|
|
|
|
def int_masked_scatter: Intrinsic<[],
|
|
[llvm_anyvector_ty,
|
|
LLVMVectorOfPointersToElt<0>, llvm_i32_ty,
|
|
LLVMVectorSameWidth<0, llvm_i1_ty>],
|
|
[IntrReadWriteArgMem]>;
|
|
|
|
// Intrinsics to support bit sets.
|
|
def int_bitset_test : Intrinsic<[llvm_i1_ty], [llvm_ptr_ty, llvm_metadata_ty],
|
|
[IntrNoMem]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target-specific intrinsics
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/IR/IntrinsicsPowerPC.td"
|
|
include "llvm/IR/IntrinsicsX86.td"
|
|
include "llvm/IR/IntrinsicsARM.td"
|
|
include "llvm/IR/IntrinsicsAArch64.td"
|
|
include "llvm/IR/IntrinsicsXCore.td"
|
|
include "llvm/IR/IntrinsicsHexagon.td"
|
|
include "llvm/IR/IntrinsicsNVVM.td"
|
|
include "llvm/IR/IntrinsicsMips.td"
|
|
include "llvm/IR/IntrinsicsR600.td"
|
|
include "llvm/IR/IntrinsicsBPF.td"
|
|
include "llvm/IR/IntrinsicsSystemZ.td"
|