Craig Topper f374109a33 [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem ... Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639		2017-10-01 23:53:53 +00:00
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avx-512.txt	[X86] Adding vpopcntd and vpopcntq instructions	2017-05-25 13:45:23 +00:00
fp-stack.txt
hex-immediates.txt
intel-syntax-32.txt
intel-syntax.txt
invalid-VEX-vvvv.txt
lit.local.cfg
marked-up.txt
missing-sib.txt
moffs.txt
padlock.txt
prefixes.txt	Revert "The current version of LLVM X86 disassembler incorrectly interprets some possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs." temporarily while some regressions are addressed.	2017-08-29 08:23:46 +00:00
simple-tests.txt
truncated-input.txt
x86-16.txt	[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem	2017-10-01 23:53:53 +00:00
x86-32.txt	[X86] Add register form of NOPL and NOPW for assembler/disassembler.	2017-07-22 01:30:51 +00:00
x86-64-err.txt	'into' instruction should not be decoded as a valid instr in 64-bit mode	2017-09-20 08:17:17 +00:00
x86-64.txt	[X86] Add nopq instruction which is a rex encoded version of nopl for gas compatibility.	2017-07-22 01:30:53 +00:00