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342fca5b08
Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 llvm-svn: 274856
105 lines
3.2 KiB
C++
105 lines
3.2 KiB
C++
//===-- SparcSubtarget.cpp - SPARC Subtarget Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SPARC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcSubtarget.h"
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#include "Sparc.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "sparc-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "SparcGenSubtargetInfo.inc"
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void SparcSubtarget::anchor() { }
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SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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IsV9 = false;
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IsLeon = false;
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V8DeprecatedInsts = false;
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IsVIS = false;
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HasHardQuad = false;
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UsePopc = false;
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UseSoftFloat = false;
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// Leon features
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HasLeonCasa = false;
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HasUmacSmac = false;
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PerformSDIVReplace = false;
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FixCallImmediates = false;
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IgnoreZeroFlag = false;
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InsertNOPDoublePrecision = false;
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FixFSMULD = false;
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ReplaceFMULS = false;
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PreventRoundChange = false;
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FixAllFDIVSQRT = false;
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InsertNOPLoad = false;
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FlushCacheLineSWAP = false;
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InsertNOPsLoadStore = false;
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// Determine default and user specified characteristics
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = (Is64Bit) ? "v9" : "v8";
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FS);
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// Popc is a v9-only instruction.
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if (!IsV9)
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UsePopc = false;
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return *this;
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}
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SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, const TargetMachine &TM,
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bool is64Bit)
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: SparcGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), Is64Bit(is64Bit),
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InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
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FrameLowering(*this) {}
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int SparcSubtarget::getAdjustedFrameSize(int frameSize) const {
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if (is64Bit()) {
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// All 64-bit stack frames must be 16-byte aligned, and must reserve space
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// for spilling the 16 window registers at %sp+BIAS..%sp+BIAS+128.
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frameSize += 128;
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// Frames with calls must also reserve space for 6 outgoing arguments
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// whether they are used or not. LowerCall_64 takes care of that.
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frameSize = alignTo(frameSize, 16);
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} else {
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// Emit the correct save instruction based on the number of bytes in
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// the frame. Minimum stack frame size according to V8 ABI is:
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// 16 words for register window spill
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// 1 word for address of returned aggregate-value
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// + 6 words for passing parameters on the stack
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// ----------
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// 23 words * 4 bytes per word = 92 bytes
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frameSize += 92;
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// Round up to next doubleword boundary -- a double-word boundary
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// is required by the ABI.
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frameSize = alignTo(frameSize, 8);
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}
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return frameSize;
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}
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bool SparcSubtarget::enableMachineScheduler() const {
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return true;
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}
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