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The z13 vector facility includes some instructions that operate only on the high f64 in a v2f64, effectively extending the FP register set from 16 to 32 registers. It's still better to use the old instructions if the operands happen to fit though, since the older instructions have a shorter encoding. Based on a patch by Richard Sandiford. llvm-svn: 236524
59 lines
1.4 KiB
LLVM
59 lines
1.4 KiB
LLVM
; Test vector negation.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a v16i8 negation.
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define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val) {
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; CHECK-LABEL: f1:
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; CHECK: vlcb %v24, %v26
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; CHECK: br %r14
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%ret = sub <16 x i8> zeroinitializer, %val
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ret <16 x i8> %ret
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}
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; Test a v8i16 negation.
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define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val) {
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; CHECK-LABEL: f2:
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; CHECK: vlch %v24, %v26
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; CHECK: br %r14
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%ret = sub <8 x i16> zeroinitializer, %val
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ret <8 x i16> %ret
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}
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; Test a v4i32 negation.
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define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val) {
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; CHECK-LABEL: f3:
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; CHECK: vlcf %v24, %v26
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; CHECK: br %r14
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%ret = sub <4 x i32> zeroinitializer, %val
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ret <4 x i32> %ret
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}
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; Test a v2i64 negation.
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define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val) {
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; CHECK-LABEL: f4:
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; CHECK: vlcg %v24, %v26
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; CHECK: br %r14
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%ret = sub <2 x i64> zeroinitializer, %val
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ret <2 x i64> %ret
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}
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; Test a v2f64 negation.
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define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val) {
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; CHECK-LABEL: f5:
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; CHECK: vflcdb %v24, %v26
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; CHECK: br %r14
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%ret = fsub <2 x double> <double -0.0, double -0.0>, %val
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ret <2 x double> %ret
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}
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; Test an f64 negation that uses vector registers.
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define double @f6(<2 x double> %val) {
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; CHECK-LABEL: f6:
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; CHECK: wflcdb %f0, %v24
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; CHECK: br %r14
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%scalar = extractelement <2 x double> %val, i32 0
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%ret = fsub double -0.0, %scalar
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ret double %ret
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}
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