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This folds (ashr (shl a, [56,48,32,24,16]), SarConst) into (shl, (sext (a), [56,48,32,24,16] - SarConst)) or into (lshr, (sext (a), SarConst - [56,48,32,24,16])) depending on sign of (SarConst - [56,48,32,24,16]) sexts in X86 are MOVs. The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size). However the MOVs have 2 advantages to SHIFTs on x86: 1. MOVs can write to a register that differs from source. 2. MOVs accept memory operands. This fixes PR24373. Patch by: evgeny.v.stupachenko@intel.com Differential Revision: http://reviews.llvm.org/D13161 llvm-svn: 255761
38 lines
861 B
LLVM
38 lines
861 B
LLVM
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
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define i32 @shl16sar15(i32 %a) #0 {
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; CHECK-LABEL: shl16sar15:
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; CHECK: # BB#0:
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; CHECK-NEXT: movswl {{[0-9]+}}(%esp), %eax
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%1 = shl i32 %a, 16
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%2 = ashr exact i32 %1, 15
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ret i32 %2
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}
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define i32 @shl16sar17(i32 %a) #0 {
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; CHECK-LABEL: shl16sar17:
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; CHECK: # BB#0:
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; CHECK-NEXT: movswl {{[0-9]+}}(%esp), %eax
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%1 = shl i32 %a, 16
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%2 = ashr exact i32 %1, 17
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ret i32 %2
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}
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define i32 @shl24sar23(i32 %a) #0 {
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; CHECK-LABEL: shl24sar23:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsbl {{[0-9]+}}(%esp), %eax
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%1 = shl i32 %a, 24
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%2 = ashr exact i32 %1, 23
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ret i32 %2
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}
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define i32 @shl24sar25(i32 %a) #0 {
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; CHECK-LABEL: shl24sar25:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsbl {{[0-9]+}}(%esp), %eax
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%1 = shl i32 %a, 24
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%2 = ashr exact i32 %1, 25
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ret i32 %2
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}
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