Craig Topper f41154b488 [AVX-512] Teach two address instruction pass to replace masked move instructions with blendm instructions when its beneficial. ... Isel now selects masked move instructions for vselect instead of blendm. But sometimes it beneficial to register allocation to remove the tied register constraint by using blendm instructions. This also picks up cases where the masked move was created due to a masked load intrinsic. Differential Revision: https://reviews.llvm.org/D28454 llvm-svn: 292005		2017-01-14 07:50:52 +00:00
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AArch64	[GlobalISel] track predecessor mapping during switch lowering.	2017-01-13 23:11:37 +00:00
AMDGPU	[AMDGPU] Implement f16 fcopysign and fcopysign(f32, f64)	2017-01-13 19:49:25 +00:00
ARM	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
AVR	[AVR] Implement TargetLoweing::getRegisterByName	2017-01-07 23:39:47 +00:00
BPF
Generic	Track validity of pass results	2017-01-13 06:09:54 +00:00
Hexagon
Inputs
Lanai
Mips	Track validity of pass results	2017-01-13 06:09:54 +00:00
MIR
MSP430
NVPTX	[NVPTX] Added support for half-precision floating point.	2017-01-13 20:56:17 +00:00
PowerPC	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
SPARC	Check for register clobbers when merging a vreg live range with a	2017-01-13 19:08:36 +00:00
SystemZ	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
Thumb	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
Thumb2	ARM: match GCC's behaviour for builtins	2017-01-13 16:25:33 +00:00
WebAssembly	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
WinEH
X86	[AVX-512] Teach two address instruction pass to replace masked move instructions with blendm instructions when its beneficial.	2017-01-14 07:50:52 +00:00
XCore