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f418c98924
Passes to fix three hardware errata that appear on some LEON processor variants. The instructions FSMULD, FMULS and FDIVS do not work as expected on some LEON processors. This change allows those instructions to be substituted for alternatives instruction sequences that are known to work. These passes only run when selected individually, or as part of a processor defintion. They are not included in general SPARC processor compilations for non-LEON processors or for those LEON processors that do not have these hardware errata. llvm-svn: 273108
93 lines
2.8 KiB
C++
Executable File
93 lines
2.8 KiB
C++
Executable File
//===------- LeonPasses.h - Define passes specific to LEON ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
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#define LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "Sparc.h"
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#include "SparcSubtarget.h"
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namespace llvm {
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class LLVM_LIBRARY_VISIBILITY LEONMachineFunctionPass
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: public MachineFunctionPass {
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protected:
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const SparcSubtarget *Subtarget;
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const int LAST_OPERAND = -1;
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//this vector holds free registers that we allocate in groups for some of the LEON passes
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std::vector <int> UsedRegisters;
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protected:
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LEONMachineFunctionPass(TargetMachine &tm, char& ID);
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LEONMachineFunctionPass(char& ID);
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int GetRegIndexForOperand(MachineInstr& MI, int OperandIndex);
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void clearUsedRegisterList();
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void markRegisterUsed(int registerIndex);
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int getUnusedFPRegister(MachineRegisterInfo& MRI);
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};
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class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass {
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public:
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static char ID;
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InsertNOPLoad(TargetMachine &tm);
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bool runOnMachineFunction(MachineFunction& MF) override;
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const char *getPassName() const override {
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return "InsertNOPLoad: Erratum Fix LBR35: insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction";
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}
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};
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class LLVM_LIBRARY_VISIBILITY FixFSMULD : public LEONMachineFunctionPass {
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public:
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static char ID;
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FixFSMULD(TargetMachine &tm);
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bool runOnMachineFunction(MachineFunction& MF) override;
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const char *getPassName() const override {
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return "FixFSMULD: Erratum Fix LBR31: do not select FSMULD";
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}
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};
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class LLVM_LIBRARY_VISIBILITY ReplaceFMULS : public LEONMachineFunctionPass {
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public:
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static char ID;
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ReplaceFMULS(TargetMachine &tm);
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bool runOnMachineFunction(MachineFunction& MF) override;
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const char *getPassName() const override {
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return "ReplaceFMULS: Erratum Fix LBR32: replace FMULS instruction with a routine using conversions/double precision operations to replace FMULS";
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}
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};
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class LLVM_LIBRARY_VISIBILITY FixAllFDIVSQRT : public LEONMachineFunctionPass {
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public:
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static char ID;
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FixAllFDIVSQRT(TargetMachine &tm);
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bool runOnMachineFunction(MachineFunction& MF) override;
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const char *getPassName() const override {
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return "FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store";
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}
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};
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} // namespace llvm
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#endif
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