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6472ad3426
If the loaded type sizes don't match the element type of the sequential type, all bets are off and the addresses may, indeed, overlap. Surprisingly, this just got caught in one test, on one builder, out of the 30+ builders testing this change. Congratulations go to http://lab.llvm.org:8011/builders/clang-aarch64-lnt/builds/5205. llvm-svn: 251112
55 lines
1.9 KiB
LLVM
55 lines
1.9 KiB
LLVM
; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output 2>&1 | FileCheck %s
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; CHECK: Function: t1
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; CHECK: NoAlias: i32* %gep1, i32* %gep2
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define void @t1([8 x i32]* %p, i32 %addend, i32* %q) {
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%knownnonzero = load i32, i32* %q, !range !0
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%add = add nsw nuw i32 %addend, %knownnonzero
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%gep1 = getelementptr [8 x i32], [8 x i32]* %p, i32 2, i32 %addend
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%gep2 = getelementptr [8 x i32], [8 x i32]* %p, i32 2, i32 %add
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ret void
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}
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; CHECK: Function: t2
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; CHECK: PartialAlias: i32* %gep1, i32* %gep2
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define void @t2([8 x i32]* %p, i32 %addend, i32* %q) {
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%knownnonzero = load i32, i32* %q, !range !0
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%add = add nsw nuw i32 %addend, %knownnonzero
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%gep1 = getelementptr [8 x i32], [8 x i32]* %p, i32 1, i32 %addend
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%gep2 = getelementptr [8 x i32], [8 x i32]* %p, i32 0, i32 %add
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ret void
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}
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; CHECK: Function: t3
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; CHECK: MustAlias: i32* %gep1, i32* %gep2
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define void @t3([8 x i32]* %p, i32 %addend, i32* %q) {
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%knownnonzero = load i32, i32* %q, !range !0
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%add = add nsw nuw i32 %addend, %knownnonzero
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%gep1 = getelementptr [8 x i32], [8 x i32]* %p, i32 0, i32 %add
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%gep2 = getelementptr [8 x i32], [8 x i32]* %p, i32 0, i32 %add
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ret void
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}
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; CHECK: Function: t4
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; CHECK: PartialAlias: i32* %gep1, i32* %gep2
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define void @t4([8 x i32]* %p, i32 %addend, i32* %q) {
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%knownnonzero = load i32, i32* %q, !range !0
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%add = add nsw nuw i32 %addend, %knownnonzero
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%gep1 = getelementptr [8 x i32], [8 x i32]* %p, i32 1, i32 %addend
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%gep2 = getelementptr [8 x i32], [8 x i32]* %p, i32 %add, i32 %add
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ret void
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}
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; CHECK: Function: t5
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; CHECK: PartialAlias: i32* %gep2, i64* %bc
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define void @t5([8 x i32]* %p, i32 %addend, i32* %q) {
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%knownnonzero = load i32, i32* %q, !range !0
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%add = add nsw nuw i32 %addend, %knownnonzero
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%gep1 = getelementptr [8 x i32], [8 x i32]* %p, i32 2, i32 %addend
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%gep2 = getelementptr [8 x i32], [8 x i32]* %p, i32 2, i32 %add
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%bc = bitcast i32* %gep1 to i64*
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ret void
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}
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!0 = !{ i32 1, i32 5 }
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