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llvm-mirror/test/Transforms/InterleavedAccess
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David Green db73d35912 [ARM] Disable VLD4 under MVE 
Alas, using half the available vector registers in a single instruction
is just too much for the register allocator to handle. The mve-vldst4.ll
test here fails when these instructions are enabled at present. This
patch disables the generation of VLD4 and VST4 by adding a
mve-max-interleave-factor option, which we currently default to 2.

Differential Revision: https://reviews.llvm.org/D71109
2019-12-08 10:37:29 +00:00
..
AArch64
ARM [ARM] Disable VLD4 under MVE 2019-12-08 10:37:29 +00:00
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