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https://github.com/RPCS3/llvm-mirror.git
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278 lines
8.4 KiB
LLVM
278 lines
8.4 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vaddi8:
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;CHECK: vadd.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = add <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vaddi16:
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;CHECK: vadd.i16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = add <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vaddi32:
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;CHECK: vadd.i32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = add <2 x i32> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vaddi64:
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;CHECK: vadd.i64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = add <1 x i64> %tmp1, %tmp2
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ret <1 x i64> %tmp3
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}
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define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vaddf32:
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;CHECK: vadd.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = add <2 x float> %tmp1, %tmp2
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ret <2 x float> %tmp3
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}
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define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vaddQi8:
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;CHECK: vadd.i8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = add <16 x i8> %tmp1, %tmp2
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vaddQi16:
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;CHECK: vadd.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = add <8 x i16> %tmp1, %tmp2
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vaddQi32:
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;CHECK: vadd.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = add <4 x i32> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vaddQi64:
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;CHECK: vadd.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = add <2 x i64> %tmp1, %tmp2
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ret <2 x i64> %tmp3
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}
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define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vaddQf32:
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;CHECK: vadd.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = add <4 x float> %tmp1, %tmp2
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ret <4 x float> %tmp3
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}
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define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vaddhni16:
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;CHECK: vaddhn.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vaddhni32:
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;CHECK: vaddhn.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vaddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vaddhni64:
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;CHECK: vaddhn.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i32> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vraddhni16:
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;CHECK: vraddhn.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vraddhni32:
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;CHECK: vraddhn.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vraddhni64:
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;CHECK: vraddhn.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i32> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vaddls8:
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;CHECK: vaddl.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vaddls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vaddls16:
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;CHECK: vaddl.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vaddls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vaddls32:
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;CHECK: vaddl.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vaddls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vaddlu8:
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;CHECK: vaddl.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vaddlu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vaddlu16:
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;CHECK: vaddl.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vaddlu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vaddlu32:
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;CHECK: vaddl.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vaddlu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <8 x i16> @llvm.arm.neon.vaddls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vaddls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vaddls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vaddlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vaddlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vaddlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
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define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vaddws8:
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;CHECK: vaddw.s8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vaddws.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vaddws16:
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;CHECK: vaddw.s16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vaddws.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vaddws32:
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;CHECK: vaddw.s32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vaddws.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vaddwu8:
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;CHECK: vaddw.u8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vaddwu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vaddwu16:
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;CHECK: vaddw.u16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vaddwu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vaddwu32:
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;CHECK: vaddw.u32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vaddwu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <8 x i16> @llvm.arm.neon.vaddws.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vaddws.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vaddws.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vaddwu.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vaddwu.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vaddwu.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
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