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https://github.com/RPCS3/llvm-mirror.git
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7a78fa03a9
Similar to D72215 (AArch64) and D72220 (x86).
```
% clang -target riscv32 -march=rv64g -c -fpatchable-function-entry=2 a.c && llvm-objdump -dr a.o
...
0000000000000000 <main>:
0: 13 00 00 00 nop
4: 13 00 00 00 nop
% clang -target riscv32 -march=rv64gc -c -fpatchable-function-entry=2 a.c && llvm-objdump -dr a.o
...
00000002 <main>:
2: 01 00 nop
4: 01 00 nop
```
Recently the mainline kernel started to use -fpatchable-function-entry=8 for riscv (https://git.kernel.org/linus/afc76b8b80112189b6f11e67e19cf58301944814).
Differential Revision: https://reviews.llvm.org/D98610
168 lines
6.5 KiB
C++
168 lines
6.5 KiB
C++
//===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
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#include "RISCVRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "RISCVGenInstrInfo.inc"
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namespace llvm {
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class RISCVSubtarget;
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class RISCVInstrInfo : public RISCVGenInstrInfo {
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public:
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explicit RISCVInstrInfo(RISCVSubtarget &STI);
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MCInst getNop() const override;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register SrcReg,
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bool IsKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register DstReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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// Materializes the given integer Val into DstReg.
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void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, Register DstReg, uint64_t Val,
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MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &dl,
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int *BytesAdded = nullptr) const override;
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unsigned insertIndirectBranch(MachineBasicBlock &MBB,
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MachineBasicBlock &NewDestBB,
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const DebugLoc &DL, int64_t BrOffset,
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RegScavenger *RS = nullptr) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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bool isAsCheapAsAMove(const MachineInstr &MI) const override;
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Optional<DestSourcePair>
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isCopyInstrImpl(const MachineInstr &MI) const override;
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bool verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const override;
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bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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const MachineOperand *&BaseOp,
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int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const;
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bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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const MachineInstr &MIb) const override;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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// Return true if the function can safely be outlined from.
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virtual bool
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isFunctionSafeToOutlineFrom(MachineFunction &MF,
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bool OutlineFromLinkOnceODRs) const override;
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// Return true if MBB is safe to outline from, and return any target-specific
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// information in Flags.
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virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
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unsigned &Flags) const override;
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// Calculate target-specific information for a set of outlining candidates.
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outliner::OutlinedFunction getOutliningCandidateInfo(
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std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
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// Return if/how a given MachineInstr should be outlined.
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virtual outliner::InstrType
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getOutliningType(MachineBasicBlock::iterator &MBBI,
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unsigned Flags) const override;
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// Insert a custom frame for outlined functions.
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virtual void
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buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
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const outliner::OutlinedFunction &OF) const override;
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// Insert a call to an outlined function into a given basic block.
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virtual MachineBasicBlock::iterator
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insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &It, MachineFunction &MF,
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const outliner::Candidate &C) const override;
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bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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Register getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II,
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int64_t Amount) const;
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protected:
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const RISCVSubtarget &STI;
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};
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namespace RISCVVPseudosTable {
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struct PseudoInfo {
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uint16_t Pseudo;
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uint16_t BaseInstr;
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};
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#define GET_RISCVVPseudosTable_DECL
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#include "RISCVGenSearchableTables.inc"
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} // end namespace RISCVVPseudosTable
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} // end namespace llvm
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#endif
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