Craig Topper f4769ac58f [DAGCombine] Add test cases to show that DAG combining an OR of two shuffles with zero vectors doesn't work if the zero vector is the first operand of the shuffle. Fix coming in a follow up patch. ... llvm-svn: 274096		2016-06-29 03:29:09 +00:00
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AArch64	MachineScheduler: Fully compare top/bottom candidates	2016-06-25 00:23:00 +00:00
AMDGPU	AMDGPU: Fix out of bounds indirect indexing errors	2016-06-28 01:09:00 +00:00
ARM	NFC. Fix popular typo in comment 'deferencing' --> 'dereferencing'.	2016-06-28 01:45:05 +00:00
BPF
Generic
Hexagon	[Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)	2016-06-27 15:08:22 +00:00
Inputs
Lanai
Mips	[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions	2016-06-27 08:23:28 +00:00
MIR
MSP430
NVPTX	Only emit extension for zeroext/signext arguments if type is < 32 bits	2016-06-27 20:22:22 +00:00
PowerPC	MachineScheduler: Fully compare top/bottom candidates	2016-06-25 00:23:00 +00:00
SPARC	Codegen: Fix broken assumption in Tail Merge.	2016-06-24 18:16:36 +00:00
SystemZ	[SystemZ] Use NILL instruction instead of NILF where possible	2016-06-28 21:03:19 +00:00
Thumb
Thumb2	Codegen: Fix broken assumption in Tail Merge.	2016-06-24 18:16:36 +00:00
WebAssembly
WinEH
X86	[DAGCombine] Add test cases to show that DAG combining an OR of two shuffles with zero vectors doesn't work if the zero vector is the first operand of the shuffle. Fix coming in a follow up patch.	2016-06-29 03:29:09 +00:00
XCore