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3a9e77fc0f
Summary: LC can currently select scalar load for uniform memory access basing on readonly memory address space only. This restriction originated from the fact that in HW prior to VI vector and scalar caches are not coherent. With MemoryDependenceAnalysis we can check that the memory location corresponding to the memory operand of the LOAD is not clobbered along the all paths from the function entry. Reviewers: rampitec, tstellarAMD, arsenm Subscribers: wdng, arsenm, nhaehnle Differential Revision: https://reviews.llvm.org/D26917 llvm-svn: 289076
536 lines
19 KiB
TableGen
536 lines
19 KiB
TableGen
//===---- SMInstructions.td - Scalar Memory Instruction Defintions --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def smrd_offset_8 : NamedOperandU32<"SMRDOffset8",
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NamedMatchClass<"SMRDOffset8">> {
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let OperandType = "OPERAND_IMMEDIATE";
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}
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def smrd_offset_20 : NamedOperandU32<"SMRDOffset20",
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NamedMatchClass<"SMRDOffset20">> {
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let OperandType = "OPERAND_IMMEDIATE";
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}
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//===----------------------------------------------------------------------===//
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// Scalar Memory classes
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//===----------------------------------------------------------------------===//
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class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
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InstSI <outs, ins, "", pattern>,
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SIMCInstr<opName, SIEncodingFamily.NONE> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let LGKM_CNT = 1;
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let SMRD = 1;
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let mayStore = 0;
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let mayLoad = 1;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let SchedRW = [WriteSMEM];
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let SubtargetPredicate = isGCN;
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string Mnemonic = opName;
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string AsmOperands = asmOps;
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bits<1> has_sbase = 1;
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bits<1> has_sdst = 1;
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bit has_glc = 0;
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bits<1> has_offset = 1;
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bits<1> offset_is_imm = 0;
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}
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class SM_Real <SM_Pseudo ps>
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: InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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// copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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// encoding
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bits<7> sbase;
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bits<7> sdst;
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bits<32> offset;
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bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0);
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}
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class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]>
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: SM_Pseudo<opName, outs, ins, asmOps, pattern> {
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RegisterClass BaseClass;
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let mayLoad = 1;
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let mayStore = 0;
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let has_glc = 1;
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}
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class SM_Store_Pseudo <string opName, dag ins, string asmOps, list<dag> pattern = []>
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: SM_Pseudo<opName, (outs), ins, asmOps, pattern> {
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RegisterClass BaseClass;
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RegisterClass SrcClass;
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let mayLoad = 0;
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let mayStore = 1;
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let has_glc = 1;
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let ScalarStore = 1;
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}
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multiclass SM_Pseudo_Loads<string opName,
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RegisterClass baseClass,
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RegisterClass dstClass> {
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def _IMM : SM_Load_Pseudo <opName,
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(outs dstClass:$sdst),
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(ins baseClass:$sbase, i32imm:$offset, i1imm:$glc),
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" $sdst, $sbase, $offset$glc", []> {
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let offset_is_imm = 1;
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let BaseClass = baseClass;
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let PseudoInstr = opName # "_IMM";
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let has_glc = 1;
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}
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def _SGPR : SM_Load_Pseudo <opName,
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(outs dstClass:$sdst),
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(ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc),
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" $sdst, $sbase, $offset$glc", []> {
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let BaseClass = baseClass;
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let PseudoInstr = opName # "_SGPR";
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let has_glc = 1;
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}
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}
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multiclass SM_Pseudo_Stores<string opName,
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RegisterClass baseClass,
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RegisterClass srcClass> {
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def _IMM : SM_Store_Pseudo <opName,
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(ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc),
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" $sdata, $sbase, $offset$glc", []> {
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let offset_is_imm = 1;
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let BaseClass = baseClass;
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let SrcClass = srcClass;
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let PseudoInstr = opName # "_IMM";
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}
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def _SGPR : SM_Store_Pseudo <opName,
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(ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc),
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" $sdata, $sbase, $offset$glc", []> {
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let BaseClass = baseClass;
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let SrcClass = srcClass;
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let PseudoInstr = opName # "_SGPR";
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}
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}
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class SM_Time_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
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opName, (outs SReg_64_XEXEC:$sdst), (ins),
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" $sdst", [(set i64:$sdst, (node))]> {
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let hasSideEffects = 1;
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// FIXME: mayStore = ? is a workaround for tablegen bug for different
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// inferred mayStore flags for the instruction pattern vs. standalone
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// Pat. Each considers the other contradictory.
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let mayStore = ?;
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let mayLoad = ?;
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let has_sbase = 0;
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let has_offset = 0;
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}
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class SM_Inval_Pseudo <string opName, SDPatternOperator node> : SM_Pseudo<
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opName, (outs), (ins), "", [(node)]> {
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let hasSideEffects = 1;
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let mayStore = 1;
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let has_sdst = 0;
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let has_sbase = 0;
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let has_offset = 0;
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}
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//===----------------------------------------------------------------------===//
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// Scalar Memory Instructions
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//===----------------------------------------------------------------------===//
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// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
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// SMRD instructions, because the SReg_32_XM0 register class does not include M0
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// and writing to M0 from an SMRD instruction will hang the GPU.
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// XXX - SMEM instructions do not allow exec for data operand, but
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// does sdst for SMRD on SI/CI?
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defm S_LOAD_DWORD : SM_Pseudo_Loads <"s_load_dword", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_load_dwordx2", SReg_64, SReg_64_XEXEC>;
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defm S_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_load_dwordx4", SReg_64, SReg_128>;
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defm S_LOAD_DWORDX8 : SM_Pseudo_Loads <"s_load_dwordx8", SReg_64, SReg_256>;
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defm S_LOAD_DWORDX16 : SM_Pseudo_Loads <"s_load_dwordx16", SReg_64, SReg_512>;
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defm S_BUFFER_LOAD_DWORD : SM_Pseudo_Loads <
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"s_buffer_load_dword", SReg_128, SReg_32_XM0_XEXEC
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>;
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// FIXME: exec_lo/exec_hi appear to be allowed for SMRD loads on
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// SI/CI, bit disallowed for SMEM on VI.
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defm S_BUFFER_LOAD_DWORDX2 : SM_Pseudo_Loads <
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"s_buffer_load_dwordx2", SReg_128, SReg_64_XEXEC
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>;
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defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads <
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"s_buffer_load_dwordx4", SReg_128, SReg_128
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>;
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defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads <
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"s_buffer_load_dwordx8", SReg_128, SReg_256
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>;
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defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads <
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"s_buffer_load_dwordx16", SReg_128, SReg_512
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>;
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defm S_STORE_DWORD : SM_Pseudo_Stores <"s_store_dword", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_STORE_DWORDX2 : SM_Pseudo_Stores <"s_store_dwordx2", SReg_64, SReg_64_XEXEC>;
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defm S_STORE_DWORDX4 : SM_Pseudo_Stores <"s_store_dwordx4", SReg_64, SReg_128>;
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defm S_BUFFER_STORE_DWORD : SM_Pseudo_Stores <
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"s_buffer_store_dword", SReg_128, SReg_32_XM0_XEXEC
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>;
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defm S_BUFFER_STORE_DWORDX2 : SM_Pseudo_Stores <
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"s_buffer_store_dwordx2", SReg_128, SReg_64_XEXEC
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>;
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defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores <
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"s_buffer_store_dwordx4", SReg_128, SReg_128
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>;
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def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>;
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def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>;
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let SubtargetPredicate = isCIVI in {
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def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
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} // let SubtargetPredicate = isCIVI
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let SubtargetPredicate = isVI in {
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def S_DCACHE_WB : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>;
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def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
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def S_MEMREALTIME : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>;
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} // SubtargetPredicate = isVI
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//===----------------------------------------------------------------------===//
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// Scalar Memory Patterns
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//===----------------------------------------------------------------------===//
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def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
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auto Ld = cast<LoadSDNode>(N);
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return Ld->getAlignment() >= 4 &&
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((Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
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static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N)) ||
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(Subtarget->getScalarizeGlobalBehavior() && Ld->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
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static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N) &&
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static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpHasNoClobberedMemOperand(N)));
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}]>;
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def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
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def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
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def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
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def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
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def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
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def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
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let Predicates = [isGCN] in {
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multiclass SMRD_Pattern <string Instr, ValueType vt> {
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// 1. IMM offset
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def : Pat <
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(smrd_load (SMRDImm i64:$sbase, i32:$offset)),
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(vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, 0))
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>;
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// 2. SGPR offset
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def : Pat <
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(smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
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(vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, 0))
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>;
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}
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let Predicates = [isSICI] in {
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def : Pat <
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(i64 (readcyclecounter)),
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(S_MEMTIME)
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>;
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}
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// Global and constant loads can be selected to either MUBUF or SMRD
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// instructions, but SMRD instructions are faster so we want the instruction
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// selector to prefer those.
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let AddedComplexity = 100 in {
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defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
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// 1. Offset as an immediate
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def SM_LOAD_PATTERN : Pat < // name this pattern to reuse AddedComplexity on CI
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(SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
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(S_BUFFER_LOAD_DWORD_IMM $sbase, $offset, 0)
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>;
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// 2. Offset loaded in an 32bit SGPR
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def : Pat <
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(SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
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(S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset, 0)
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>;
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} // End let AddedComplexity = 100
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} // let Predicates = [isGCN]
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let Predicates = [isVI] in {
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// 1. Offset as 20bit DWORD immediate
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def : Pat <
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(SIload_constant v4i32:$sbase, IMM20bit:$offset),
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(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset), 0)
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>;
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def : Pat <
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(i64 (readcyclecounter)),
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(S_MEMREALTIME)
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>;
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} // let Predicates = [isVI]
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//===----------------------------------------------------------------------===//
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// Targets
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SI
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//===----------------------------------------------------------------------===//
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class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
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: SM_Real<ps>
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, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
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, Enc32 {
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let AssemblerPredicates = [isSICI];
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let DecoderNamespace = "SICI";
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let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
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let Inst{8} = imm;
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let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
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let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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}
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// FIXME: Assembler should reject trying to use glc on SMRD
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// instructions on SI.
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multiclass SM_Real_Loads_si<bits<5> op, string ps,
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SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
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SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
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def _IMM_si : SMRD_Real_si <op, immPs> {
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let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, GLC:$glc);
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}
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// FIXME: The operand name $offset is inconsistent with $soff used
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// in the pseudo
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def _SGPR_si : SMRD_Real_si <op, sgprPs> {
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let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
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}
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}
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defm S_LOAD_DWORD : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">;
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defm S_LOAD_DWORDX2 : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">;
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defm S_LOAD_DWORDX4 : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">;
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defm S_LOAD_DWORDX8 : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">;
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defm S_LOAD_DWORDX16 : SM_Real_Loads_si <0x04, "S_LOAD_DWORDX16">;
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defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_si <0x08, "S_BUFFER_LOAD_DWORD">;
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defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_si <0x09, "S_BUFFER_LOAD_DWORDX2">;
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defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_si <0x0a, "S_BUFFER_LOAD_DWORDX4">;
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defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_si <0x0b, "S_BUFFER_LOAD_DWORDX8">;
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defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c, "S_BUFFER_LOAD_DWORDX16">;
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def S_MEMTIME_si : SMRD_Real_si <0x1e, S_MEMTIME>;
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def S_DCACHE_INV_si : SMRD_Real_si <0x1f, S_DCACHE_INV>;
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//===----------------------------------------------------------------------===//
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// VI
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//===----------------------------------------------------------------------===//
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class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
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: SM_Real<ps>
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, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
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, Enc64 {
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bit glc;
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let AssemblerPredicates = [isVI];
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let DecoderNamespace = "VI";
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let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
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let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
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let Inst{16} = !if(ps.has_glc, glc, ?);
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let Inst{17} = imm;
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let Inst{25-18} = op;
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let Inst{31-26} = 0x30; //encoding
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let Inst{51-32} = !if(ps.has_offset, offset{19-0}, ?);
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}
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multiclass SM_Real_Loads_vi<bits<8> op, string ps,
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SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
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SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
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def _IMM_vi : SMEM_Real_vi <op, immPs> {
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let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
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}
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def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
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let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
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}
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}
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class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
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// encoding
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bits<7> sdata;
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let sdst = ?;
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let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
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}
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multiclass SM_Real_Stores_vi<bits<8> op, string ps,
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SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
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SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
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// FIXME: The operand name $offset is inconsistent with $soff used
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// in the pseudo
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def _IMM_vi : SMEM_Real_Store_vi <op, immPs> {
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let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
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}
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def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> {
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let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
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}
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}
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defm S_LOAD_DWORD : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">;
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defm S_LOAD_DWORDX2 : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">;
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defm S_LOAD_DWORDX4 : SM_Real_Loads_vi <0x02, "S_LOAD_DWORDX4">;
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defm S_LOAD_DWORDX8 : SM_Real_Loads_vi <0x03, "S_LOAD_DWORDX8">;
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defm S_LOAD_DWORDX16 : SM_Real_Loads_vi <0x04, "S_LOAD_DWORDX16">;
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defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_vi <0x08, "S_BUFFER_LOAD_DWORD">;
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defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_vi <0x09, "S_BUFFER_LOAD_DWORDX2">;
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defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_vi <0x0a, "S_BUFFER_LOAD_DWORDX4">;
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defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_vi <0x0b, "S_BUFFER_LOAD_DWORDX8">;
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defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_vi <0x0c, "S_BUFFER_LOAD_DWORDX16">;
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defm S_STORE_DWORD : SM_Real_Stores_vi <0x10, "S_STORE_DWORD">;
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defm S_STORE_DWORDX2 : SM_Real_Stores_vi <0x11, "S_STORE_DWORDX2">;
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defm S_STORE_DWORDX4 : SM_Real_Stores_vi <0x12, "S_STORE_DWORDX4">;
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defm S_BUFFER_STORE_DWORD : SM_Real_Stores_vi <0x18, "S_BUFFER_STORE_DWORD">;
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defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_vi <0x19, "S_BUFFER_STORE_DWORDX2">;
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defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_vi <0x1a, "S_BUFFER_STORE_DWORDX4">;
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// These instructions use same encoding
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def S_DCACHE_INV_vi : SMEM_Real_vi <0x20, S_DCACHE_INV>;
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def S_DCACHE_WB_vi : SMEM_Real_vi <0x21, S_DCACHE_WB>;
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def S_DCACHE_INV_VOL_vi : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>;
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def S_DCACHE_WB_VOL_vi : SMEM_Real_vi <0x23, S_DCACHE_WB_VOL>;
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def S_MEMTIME_vi : SMEM_Real_vi <0x24, S_MEMTIME>;
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def S_MEMREALTIME_vi : SMEM_Real_vi <0x25, S_MEMREALTIME>;
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//===----------------------------------------------------------------------===//
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// CI
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//===----------------------------------------------------------------------===//
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def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset",
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NamedMatchClass<"SMRDLiteralOffset">> {
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let OperandType = "OPERAND_IMMEDIATE";
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}
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class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
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SM_Real<ps>,
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Enc64 {
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let AssemblerPredicates = [isCIOnly];
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let DecoderNamespace = "CI";
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let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc);
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let LGKM_CNT = ps.LGKM_CNT;
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let SMRD = ps.SMRD;
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let mayLoad = ps.mayLoad;
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let mayStore = ps.mayStore;
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let hasSideEffects = ps.hasSideEffects;
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let SchedRW = ps.SchedRW;
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let UseNamedOperandTable = ps.UseNamedOperandTable;
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let Inst{7-0} = 0xff;
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let Inst{8} = 0;
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let Inst{14-9} = sbase{6-1};
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let Inst{21-15} = sdst{6-0};
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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let Inst{63-32} = offset{31-0};
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}
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def S_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x00, S_LOAD_DWORD_IMM>;
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def S_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x01, S_LOAD_DWORDX2_IMM>;
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def S_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x02, S_LOAD_DWORDX4_IMM>;
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def S_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x03, S_LOAD_DWORDX8_IMM>;
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def S_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x04, S_LOAD_DWORDX16_IMM>;
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def S_BUFFER_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x08, S_BUFFER_LOAD_DWORD_IMM>;
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def S_BUFFER_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x09, S_BUFFER_LOAD_DWORDX2_IMM>;
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def S_BUFFER_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x0a, S_BUFFER_LOAD_DWORDX4_IMM>;
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|
def S_BUFFER_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x0b, S_BUFFER_LOAD_DWORDX8_IMM>;
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|
def S_BUFFER_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x0c, S_BUFFER_LOAD_DWORDX16_IMM>;
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|
|
|
class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
|
|
: SM_Real<ps>
|
|
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
|
|
, Enc32 {
|
|
|
|
let AssemblerPredicates = [isCIOnly];
|
|
let DecoderNamespace = "CI";
|
|
|
|
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
|
|
let Inst{8} = imm;
|
|
let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
|
|
let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
|
|
let Inst{26-22} = op;
|
|
let Inst{31-27} = 0x18; //encoding
|
|
}
|
|
|
|
def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>;
|
|
|
|
let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity in {
|
|
|
|
class SMRD_Pattern_ci <string Instr, ValueType vt> : Pat <
|
|
(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
|
|
(vt (!cast<SM_Pseudo>(Instr#"_IMM_ci") $sbase, $offset, 0))> {
|
|
let Predicates = [isCIOnly];
|
|
}
|
|
|
|
def : SMRD_Pattern_ci <"S_LOAD_DWORD", i32>;
|
|
def : SMRD_Pattern_ci <"S_LOAD_DWORDX2", v2i32>;
|
|
def : SMRD_Pattern_ci <"S_LOAD_DWORDX4", v4i32>;
|
|
def : SMRD_Pattern_ci <"S_LOAD_DWORDX8", v8i32>;
|
|
def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>;
|
|
|
|
def : Pat <
|
|
(SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
|
|
(S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset, 0)> {
|
|
let Predicates = [isCI]; // should this be isCIOnly?
|
|
}
|
|
|
|
} // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity
|
|
|