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50947152c2
Summary of changes: - added description of MTBUF instructions and format modifier; - described limitations of f16 inline constants when used with integer operands; - updated description of gfx9+ flat global addressing modes; - v_accvgpr_write_b32 src0 corrections (gfx908); - minor bugfixing and improvements.
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1.0 KiB
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24 lines
1.0 KiB
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..
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid10_addr_mimg:
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vaddr
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===========================
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Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
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This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
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*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
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* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
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* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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