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Summary: The loop which emits AssemblerPredicate conditions also links them together by emitting a '&&'. If the 1st predicate is not an AssemblerPredicate, while the 2nd one is, nothing gets emitted for the 1st one, but we still emit the '&&' because of the 2nd predicate. This generated code looks like "( && Cond2)" and is invalid. Reviewers: dsanders Reviewed By: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D8294 llvm-svn: 234312 |
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.. | ||
2003-08-03-PassCode.td | ||
2006-09-18-LargeInt.td | ||
2010-03-24-PrematureDefaults.td | ||
AnonDefinitionOnDemand.td | ||
AsmPredicateCondsEmission.td | ||
BitOffsetDecoder.td | ||
BitsInit.td | ||
BitsInitOverflow.td | ||
cast.td | ||
ClassInstanceValue.td | ||
CStyleComment.td | ||
Dag.td | ||
defmclass.td | ||
DefmInherit.td | ||
DefmInsideMultiClass.td | ||
eq.td | ||
eqbit.td | ||
FieldAccess.td | ||
foreach.td | ||
ForeachList.td | ||
ForeachLoop.td | ||
ForwardRef.td | ||
GeneralList.td | ||
if-empty-list-arg.td | ||
if.td | ||
ifbit.td | ||
Include.inc | ||
Include.td | ||
IntBitInit.td | ||
intrinsic-long-name.td | ||
intrinsic-order.td | ||
intrinsic-varargs.td | ||
LazyChange.td | ||
LetInsideMultiClasses.td | ||
lisp.td | ||
list-element-bitref.td | ||
ListArgs.td | ||
ListArgsSimple.td | ||
listconcat.td | ||
ListConversion.td | ||
ListManip.td | ||
ListOfList.td | ||
ListSlices.td | ||
lit.local.cfg | ||
LoLoL.td | ||
math.td | ||
MultiClass.td | ||
MultiClassDefName.td | ||
MultiClassInherit.td | ||
MultiPat.td | ||
nested-comment.td | ||
NestedForeach.td | ||
Paste.td | ||
pr8330.td | ||
SetTheory.td | ||
SiblingForeach.td | ||
Slice.td | ||
strconcat.td | ||
String.td | ||
subst2.td | ||
subst.td | ||
SuperSubclassSameName.td | ||
TargetInstrInfo.td | ||
TargetInstrSpec.td | ||
TemplateArgRename.td | ||
Tree.td | ||
TreeNames.td | ||
TwoLevelName.td | ||
UnsetBitInit.td | ||
UnterminatedComment.td | ||
usevalname.td | ||
ValidIdentifiers.td |