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efb5d2ce6e
subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. llvm-svn: 54223
14 lines
395 B
LLVM
14 lines
395 B
LLVM
; RUN: llvm-as < %s | llc -march=x86 | not grep and
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; These tests differ from the ones in zext-inreg-0.ll in that
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; on x86-64 they do require and instructions.
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; These should use movzbl instead of 'and 255'.
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; This related to not having ZERO_EXTEND_REG node.
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define i64 @h(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 281474976710655
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ret i64 %retval
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}
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