Craig Topper 489536319e [X86] When post-processing the DAG to remove zero extending moves for YMM/ZMM, make sure the producing instruction is VEX/XOP/EVEX encoded. ... If the producing instruction is legacy encoded it doesn't implicitly zero the upper bits. This is important for the SHA instructions which don't have a VEX encoded version. We might also be able to hit this with the incomplete f128 support that hasn't been ported to VEX. llvm-svn: 338812		2018-08-03 04:49:42 +00:00
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AArch64	[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value	2018-08-02 08:33:31 +00:00
AMDGPU	[AMDGPU] Reworked SIFixWWMLiveness	2018-08-02 23:31:32 +00:00
ARC
ARM	[ARM][NFC] Follow up of r338568	2018-08-02 14:04:48 +00:00
AVR
BPF	bpf: add missing RegState to notify MachineInstr verifier necessary register usage	2018-07-27 16:58:52 +00:00
Generic
Hexagon	[Hexagon] Simplify CFG after atomic expansion	2018-08-02 22:17:53 +00:00
Inputs
Lanai
Mips	[MIPS GlobalISel] Select global address	2018-08-01 09:03:23 +00:00
MIR
MSP430
Nios2
NVPTX
PowerPC	[PowerPC] Do not round values prior to converting to integer	2018-08-02 00:03:22 +00:00
RISCV	[RISCV] Fixed test case failure due to r338047	2018-07-31 00:36:28 +00:00
SPARC
SystemZ	[SystemZ, TableGen] Fix shift count handling	2018-08-01 11:57:58 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Support for atomic.wait / atomic.wake instructions	2018-08-02 21:44:24 +00:00
WinCFGuard
WinEH
X86	[X86] When post-processing the DAG to remove zero extending moves for YMM/ZMM, make sure the producing instruction is VEX/XOP/EVEX encoded.	2018-08-03 04:49:42 +00:00
XCore