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dc91ae935f
The previous names were both misleading (the MachineLegalizer actually contained the info tables) and inconsistent with the selector & translator (in having a "Machine") prefix. This should make everything sensible again. The only functional change is the name of a couple of command-line options. llvm-svn: 284287
24 lines
1.0 KiB
LLVM
24 lines
1.0 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi
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; This test case tests an infinite loop bug in DAG combiner.
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; It just tries to do the following replacing endlessly:
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; (1) Replacing.3 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
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; With: 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
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;
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; (2) Replacing.2 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
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; With: 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
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; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
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; an optimization to replace unused bits with undefined bits, we remove
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; the (1) optimization (It doesn't make sense to replace undefined bits
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; with signed bits).
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define <4 x i32> @infiniteLoop(<4 x i32> %in0, <4 x i16> %in1) {
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entry:
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%cmp.i = icmp sge <4 x i16> %in1, <i16 32767, i16 32767, i16 -1, i16 -32768>
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%sext.i = sext <4 x i1> %cmp.i to <4 x i32>
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%mul.i = mul <4 x i32> %in0, %sext.i
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%sext = shl <4 x i32> %mul.i, <i32 16, i32 16, i32 16, i32 16>
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%vmovl.i.i = ashr <4 x i32> %sext, <i32 16, i32 16, i32 16, i32 16>
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ret <4 x i32> %vmovl.i.i
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}
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