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84b578a23c
Summary: performPostLD1Combine in AArch64ISelLowering looks for vector insert_vector_elt of a loaded value which it can optimize into a single LD1LANE instruction. The code checking for the pattern was not checking if the lane index was a constant which could cause two problems: - an assert when lowering the LD1LANE ISD node since it assumes an constant operand - an assert in isel if the lane index value depends on the post-incremented base register Both of these issues are avoided by simply checking that the lane index is a constant. Fixes bug 35822. Reviewers: t.p.northover, javed.absar Subscribers: rengolin, kristof.beyls, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46591 llvm-svn: 332103
63 lines
2.4 KiB
LLVM
63 lines
2.4 KiB
LLVM
; RUN: llc < %s
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; This used to assert with "Overran sorted position" in AssignTopologicalOrder
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; due to a cycle created in performPostLD1Combine.
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios7.0.0"
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; Function Attrs: nounwind ssp
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define void @f(double* %P1) #0 {
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entry:
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%arrayidx4 = getelementptr inbounds double, double* %P1, i64 1
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%0 = load double, double* %arrayidx4, align 8, !tbaa !1
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%1 = load double, double* %P1, align 8, !tbaa !1
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%2 = insertelement <2 x double> undef, double %0, i32 0
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%3 = insertelement <2 x double> %2, double %1, i32 1
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%4 = fsub <2 x double> zeroinitializer, %3
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%5 = fmul <2 x double> undef, %4
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%6 = extractelement <2 x double> %5, i32 0
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%cmp168 = fcmp olt double %6, undef
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br i1 %cmp168, label %if.then172, label %return
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if.then172: ; preds = %cond.end90
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%7 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false)
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br label %return
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return: ; preds = %if.then172, %cond.end90, %entry
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ret void
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}
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; Avoid an assert/bad codegen in LD1LANEPOST lowering by not forming
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; LD1LANEPOST ISD nodes with a non-constant lane index.
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define <4 x i32> @f2(i32 *%p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2, i32 %idx) {
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%L0 = load i32, i32* %p
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%p1 = getelementptr i32, i32* %p, i64 1
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%L1 = load i32, i32* %p1
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%v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2
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%vret = insertelement <4 x i32> %v, i32 %L0, i32 %idx
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store i32 %L1, i32 *%p
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ret <4 x i32> %vret
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}
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; Check that a cycle is avoided during isel between the LD1LANEPOST instruction and the load of %L1.
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define <4 x i32> @f3(i32 *%p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2) {
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%L0 = load i32, i32* %p
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%p1 = getelementptr i32, i32* %p, i64 1
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%L1 = load i32, i32* %p1
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%v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2
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%vret = insertelement <4 x i32> %v, i32 %L0, i32 %L1
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ret <4 x i32> %vret
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #1
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attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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!1 = !{!2, !2, i64 0}
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!2 = !{!"double", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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