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5efe040582
Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
37 lines
820 B
LLVM
37 lines
820 B
LLVM
; RUN: llc -verify-machineinstrs -aarch64-enable-atomic-cfg-tidy=0 < %s -mtriple=aarch64-none-eabihf -fast-isel=false | FileCheck %s
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define i32 @ule_64_max(i64 %p) {
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entry:
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; CHECK-LABEL: ule_64_max:
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; CHECK: cmn x0, #1
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; CHECK: b.hi [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
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%cmp = icmp ule i64 %p, 18446744073709551615 ; 0xffffffffffffffff
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br i1 %cmp, label %ret_one, label %ret_zero
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ret_one:
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ret i32 1
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ret_zero:
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; CHECK: [[RET_ZERO]]:
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; CHECK-NEXT: mov w0, wzr
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ret i32 0
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}
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define i32 @ugt_64_max(i64 %p) {
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entry:
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; CHECK-LABEL: ugt_64_max:
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; CHECK: cmn x0, #1
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; CHECK: b.ls [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
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%cmp = icmp ugt i64 %p, 18446744073709551615 ; 0xffffffffffffffff
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br i1 %cmp, label %ret_one, label %ret_zero
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ret_one:
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ret i32 1
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ret_zero:
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; CHECK: [[RET_ZERO]]:
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; CHECK-NEXT: mov w0, wzr
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ret i32 0
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}
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