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https://github.com/RPCS3/llvm-mirror.git
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c803170766
We are already falling back to SelectionDAG when encountering an shift with UB. This adds the same checks for shifts with UB that get folded into arithmetic or logical operations. This fixes rdar://problem/22345295. llvm-svn: 245499
363 lines
8.1 KiB
LLVM
363 lines
8.1 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
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; AND
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define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) {
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; CHECK-LABEL: and_rr_i1
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; CHECK: and [[REG:w[0-9]+]], w0, w1
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%1 = and i1 %a, %b
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ret i1 %1
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}
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define zeroext i8 @and_rr_i8(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: and_rr_i8
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; CHECK: and [[REG:w[0-9]+]], w0, w1
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
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%1 = and i8 %a, %b
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ret i8 %1
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}
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define zeroext i16 @and_rr_i16(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: and_rr_i16
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; CHECK: and [[REG:w[0-9]+]], w0, w1
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
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%1 = and i16 %a, %b
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ret i16 %1
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}
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define i32 @and_rr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: and_rr_i32
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; CHECK: and w0, w0, w1
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%1 = and i32 %a, %b
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ret i32 %1
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}
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define i64 @and_rr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: and_rr_i64
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; CHECK: and x0, x0, x1
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%1 = and i64 %a, %b
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ret i64 %1
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}
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define zeroext i1 @and_ri_i1(i1 signext %a) {
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; CHECK-LABEL: and_ri_i1
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; CHECK: and {{w[0-9]+}}, w0, #0x1
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%1 = and i1 %a, 1
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ret i1 %1
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}
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define zeroext i8 @and_ri_i8(i8 signext %a) {
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; CHECK-LABEL: and_ri_i8
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; CHECK: and {{w[0-9]+}}, w0, #0xf
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%1 = and i8 %a, 15
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ret i8 %1
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}
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define zeroext i16 @and_ri_i16(i16 signext %a) {
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; CHECK-LABEL: and_ri_i16
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; CHECK: and {{w[0-9]+}}, w0, #0xff
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%1 = and i16 %a, 255
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ret i16 %1
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}
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define i32 @and_ri_i32(i32 %a) {
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; CHECK-LABEL: and_ri_i32
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; CHECK: and w0, w0, #0xff
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%1 = and i32 %a, 255
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ret i32 %1
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}
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define i64 @and_ri_i64(i64 %a) {
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; CHECK-LABEL: and_ri_i64
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; CHECK: and x0, x0, #0xff
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%1 = and i64 %a, 255
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ret i64 %1
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}
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define zeroext i8 @and_rs_i8(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: and_rs_i8
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; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #4
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
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%1 = shl i8 %b, 4
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%2 = and i8 %a, %1
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ret i8 %2
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}
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define zeroext i16 @and_rs_i16(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: and_rs_i16
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; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #8
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
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%1 = shl i16 %b, 8
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%2 = and i16 %a, %1
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ret i16 %2
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}
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define i32 @and_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: and_rs_i32
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; CHECK: and w0, w0, w1, lsl #8
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%1 = shl i32 %b, 8
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%2 = and i32 %a, %1
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ret i32 %2
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}
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define i64 @and_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: and_rs_i64
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; CHECK: and x0, x0, x1, lsl #8
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%1 = shl i64 %b, 8
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%2 = and i64 %a, %1
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ret i64 %2
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}
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define i32 @and_mul_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: and_mul_i32
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; CHECK: and w0, w0, w1, lsl #2
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%1 = mul i32 %b, 4
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%2 = and i32 %a, %1
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ret i32 %2
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}
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define i64 @and_mul_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: and_mul_i64
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; CHECK: and x0, x0, x1, lsl #2
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%1 = mul i64 %b, 4
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%2 = and i64 %a, %1
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ret i64 %2
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}
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; OR
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define zeroext i1 @or_rr_i1(i1 signext %a, i1 signext %b) {
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; CHECK-LABEL: or_rr_i1
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; CHECK: orr [[REG:w[0-9]+]], w0, w1
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%1 = or i1 %a, %b
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ret i1 %1
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}
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define zeroext i8 @or_rr_i8(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: or_rr_i8
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; CHECK: orr [[REG:w[0-9]+]], w0, w1
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
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%1 = or i8 %a, %b
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ret i8 %1
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}
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define zeroext i16 @or_rr_i16(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: or_rr_i16
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; CHECK: orr [[REG:w[0-9]+]], w0, w1
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
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%1 = or i16 %a, %b
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ret i16 %1
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}
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define i32 @or_rr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: or_rr_i32
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; CHECK: orr w0, w0, w1
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%1 = or i32 %a, %b
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ret i32 %1
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}
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define i64 @or_rr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: or_rr_i64
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; CHECK: orr x0, x0, x1
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%1 = or i64 %a, %b
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ret i64 %1
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}
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define zeroext i8 @or_ri_i8(i8 %a) {
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; CHECK-LABEL: or_ri_i8
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; CHECK: orr [[REG:w[0-9]+]], w0, #0xf
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
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%1 = or i8 %a, 15
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ret i8 %1
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}
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define zeroext i16 @or_ri_i16(i16 %a) {
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; CHECK-LABEL: or_ri_i16
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; CHECK: orr [[REG:w[0-9]+]], w0, #0xff
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
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%1 = or i16 %a, 255
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ret i16 %1
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}
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define i32 @or_ri_i32(i32 %a) {
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; CHECK-LABEL: or_ri_i32
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; CHECK: orr w0, w0, #0xff
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%1 = or i32 %a, 255
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ret i32 %1
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}
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define i64 @or_ri_i64(i64 %a) {
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; CHECK-LABEL: or_ri_i64
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; CHECK: orr x0, x0, #0xff
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%1 = or i64 %a, 255
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ret i64 %1
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}
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define zeroext i8 @or_rs_i8(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: or_rs_i8
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; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #4
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
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%1 = shl i8 %b, 4
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%2 = or i8 %a, %1
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ret i8 %2
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}
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define zeroext i16 @or_rs_i16(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: or_rs_i16
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; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #8
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
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%1 = shl i16 %b, 8
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%2 = or i16 %a, %1
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ret i16 %2
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}
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define i32 @or_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: or_rs_i32
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; CHECK: orr w0, w0, w1, lsl #8
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%1 = shl i32 %b, 8
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%2 = or i32 %a, %1
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ret i32 %2
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}
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define i64 @or_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: or_rs_i64
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; CHECK: orr x0, x0, x1, lsl #8
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%1 = shl i64 %b, 8
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%2 = or i64 %a, %1
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ret i64 %2
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}
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define i32 @or_mul_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: or_mul_i32
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; CHECK: orr w0, w0, w1, lsl #2
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%1 = mul i32 %b, 4
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%2 = or i32 %a, %1
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ret i32 %2
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}
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define i64 @or_mul_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: or_mul_i64
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; CHECK: orr x0, x0, x1, lsl #2
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%1 = mul i64 %b, 4
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%2 = or i64 %a, %1
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ret i64 %2
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}
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; XOR
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define zeroext i1 @xor_rr_i1(i1 signext %a, i1 signext %b) {
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; CHECK-LABEL: xor_rr_i1
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; CHECK: eor [[REG:w[0-9]+]], w0, w1
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%1 = xor i1 %a, %b
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ret i1 %1
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}
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define zeroext i8 @xor_rr_i8(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: xor_rr_i8
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; CHECK: eor [[REG:w[0-9]+]], w0, w1
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
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%1 = xor i8 %a, %b
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ret i8 %1
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}
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define zeroext i16 @xor_rr_i16(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: xor_rr_i16
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; CHECK: eor [[REG:w[0-9]+]], w0, w1
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
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%1 = xor i16 %a, %b
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ret i16 %1
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}
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define i32 @xor_rr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: xor_rr_i32
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; CHECK: eor w0, w0, w1
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%1 = xor i32 %a, %b
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ret i32 %1
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}
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define i64 @xor_rr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: xor_rr_i64
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; CHECK: eor x0, x0, x1
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%1 = xor i64 %a, %b
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ret i64 %1
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}
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define zeroext i8 @xor_ri_i8(i8 signext %a) {
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; CHECK-LABEL: xor_ri_i8
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; CHECK: eor [[REG:w[0-9]+]], w0, #0xf
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
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%1 = xor i8 %a, 15
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ret i8 %1
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}
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define zeroext i16 @xor_ri_i16(i16 signext %a) {
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; CHECK-LABEL: xor_ri_i16
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; CHECK: eor [[REG:w[0-9]+]], w0, #0xff
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
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%1 = xor i16 %a, 255
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ret i16 %1
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}
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define i32 @xor_ri_i32(i32 %a) {
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; CHECK-LABEL: xor_ri_i32
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; CHECK: eor w0, w0, #0xff
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%1 = xor i32 %a, 255
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ret i32 %1
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}
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define i64 @xor_ri_i64(i64 %a) {
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; CHECK-LABEL: xor_ri_i64
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; CHECK: eor x0, x0, #0xff
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%1 = xor i64 %a, 255
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ret i64 %1
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}
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define zeroext i8 @xor_rs_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: xor_rs_i8
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; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #4
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
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%1 = shl i8 %b, 4
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%2 = xor i8 %a, %1
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ret i8 %2
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}
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define zeroext i16 @xor_rs_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: xor_rs_i16
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; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #8
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
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%1 = shl i16 %b, 8
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%2 = xor i16 %a, %1
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ret i16 %2
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}
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define i32 @xor_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: xor_rs_i32
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; CHECK: eor w0, w0, w1, lsl #8
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%1 = shl i32 %b, 8
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%2 = xor i32 %a, %1
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ret i32 %2
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}
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define i64 @xor_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: xor_rs_i64
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; CHECK: eor x0, x0, x1, lsl #8
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%1 = shl i64 %b, 8
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%2 = xor i64 %a, %1
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ret i64 %2
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}
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define i32 @xor_mul_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: xor_mul_i32
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; CHECK: eor w0, w0, w1, lsl #2
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%1 = mul i32 %b, 4
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%2 = xor i32 %a, %1
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ret i32 %2
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}
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define i64 @xor_mul_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: xor_mul_i64
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; CHECK: eor x0, x0, x1, lsl #2
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%1 = mul i64 %b, 4
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%2 = xor i64 %a, %1
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ret i64 %2
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}
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