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2a100074b2
The NewNodesMustHaveLegalTypes flag is set to false at the beginning of CodeGenAndEmitDAG, and set to true after legalizing types. But before calling CodeGenAndEmitDAG we build the DAG for the basic block. So for the first basic block NewNodesMustHaveLegalTypes would be 'false' during the SDAG building, and for all other basic blocks it would be 'true'. This patch sets the flag to false before SDAG building each basic block. Differential Revision: https://reviews.llvm.org/D33435 llvm-svn: 310239
45 lines
1.8 KiB
LLVM
45 lines
1.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
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define i64 @dotests_616() {
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; CHECK-LABEL: dotests_616
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; CHECK: movi d0, #0000000000000000
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <2 x i64> zeroinitializer to <8 x i16>
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%1 = and <8 x i16> zeroinitializer, %0
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%2 = icmp ne <8 x i16> %1, zeroinitializer
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%3 = extractelement <8 x i1> %2, i32 2
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%vgetq_lane285 = sext i1 %3 to i16
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%vset_lane = insertelement <4 x i16> undef, i16 %vgetq_lane285, i32 0
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%4 = bitcast <4 x i16> %vset_lane to <1 x i64>
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%vget_lane = extractelement <1 x i64> %4, i32 0
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ret i64 %vget_lane
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}
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; PR25763 - folding constant vector comparisons with sign-extended result
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define <8 x i16> @dotests_458() {
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; CHECK-LABEL: .LCPI1_0:
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; CHECK: .hword 0 // 0x0
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; CHECK-NEXT: .hword 0 // 0x0
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; CHECK-NEXT: .hword 65535 // 0xffff
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; CHECK-NEXT: .hword 0 // 0x0
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; CHECK-NEXT: .hword 0 // 0x0
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; CHECK-NEXT: .hword 0 // 0x0
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; CHECK-NEXT: .hword 0 // 0x0
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; CHECK-NEXT: .hword 0 // 0x0
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; CHECK-LABEL: dotests_458
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; CHECK: adrp x8, .LCPI1_0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: ret
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entry:
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%vclz_v.i = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> <i8 127, i8 38, i8 -1, i8 -128, i8 127, i8 0, i8 0, i8 0>, i1 false) #6
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%vsra_n = lshr <8 x i8> %vclz_v.i, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
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%name_6 = or <8 x i8> %vsra_n, <i8 127, i8 -128, i8 -1, i8 67, i8 84, i8 127, i8 -1, i8 0>
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%cmp.i603 = icmp slt <8 x i8> %name_6, <i8 -57, i8 -128, i8 127, i8 -128, i8 -1, i8 0, i8 -1, i8 -1>
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%vmovl.i4.i = sext <8 x i1> %cmp.i603 to <8 x i16>
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ret <8 x i16> %vmovl.i4.i
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}
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declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1)
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