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5efe040582
Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
49 lines
1.2 KiB
LLVM
49 lines
1.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
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; We've got the usual issues with LLVM reordering blocks here. The
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; tests are correct for the current order, but who knows when that
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; will change. Beware!
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@var32 = global i32 0
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@var64 = global i64 0
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define i32 @test_tbz() {
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; CHECK-LABEL: test_tbz:
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%val = load i32, i32* @var32
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%val64 = load i64, i64* @var64
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%tbit0 = and i32 %val, 32768
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%tst0 = icmp ne i32 %tbit0, 0
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br i1 %tst0, label %test1, label %end1
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; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.?LBB0_[0-9]+]]
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test1:
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%tbit1 = and i32 %val, 4096
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%tst1 = icmp ne i32 %tbit1, 0
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br i1 %tst1, label %test2, label %end1
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; CHECK: tbz {{w[0-9]+}}, #12, [[LBL_end1]]
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test2:
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%tbit2 = and i64 %val64, 32768
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%tst2 = icmp ne i64 %tbit2, 0
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br i1 %tst2, label %test3, label %end1
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; CHECK: tbz {{[wx][0-9]+}}, #15, [[LBL_end1]]
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test3:
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%tbit3 = and i64 %val64, 4096
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%tst3 = icmp ne i64 %tbit3, 0
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br i1 %tst3, label %end2, label %end1
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; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]]
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end2:
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; CHECK: {{movz x0, #1|orr w0, wzr, #0x1}}
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; CHECK-NEXT: ret
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ret i32 1
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end1:
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; CHECK: [[LBL_end1]]:
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; CHECK-NEXT: {{mov x0, xzr|mov w0, wzr}}
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; CHECK-NEXT: ret
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ret i32 0
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}
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